Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4215177	1			T23	1		T24	66		T25	1
all_pins[1]	4215177	1			T23	1		T24	66		T25	1
all_pins[2]	4215177	1			T23	1		T24	66		T25	1
all_pins[3]	4215177	1			T23	1		T24	66		T25	1
all_pins[4]	4215177	1			T23	1		T24	66		T25	1
all_pins[5]	4215177	1			T23	1		T24	66		T25	1
all_pins[6]	4215177	1			T23	1		T24	66		T25	1
all_pins[7]	4215177	1			T23	1		T24	66		T25	1
all_pins[8]	4215177	1			T23	1		T24	66		T25	1
all_pins[9]	4215177	1			T23	1		T24	66		T25	1
all_pins[10]	4215177	1			T23	1		T24	66		T25	1
all_pins[11]	4215177	1			T23	1		T24	66		T25	1
all_pins[12]	4215177	1			T23	1		T24	66		T25	1
all_pins[13]	4215177	1			T23	1		T24	66		T25	1
all_pins[14]	4215177	1			T23	1		T24	66		T25	1
all_pins[15]	4215177	1			T23	1		T24	66		T25	1
all_pins[16]	4215177	1			T23	1		T24	66		T25	1
all_pins[17]	4215177	1			T23	1		T24	66		T25	1
all_pins[18]	4215177	1			T23	1		T24	66		T25	1
all_pins[19]	4215177	1			T23	1		T24	66		T25	1
all_pins[20]	4215177	1			T23	1		T24	66		T25	1
all_pins[21]	4215177	1			T23	1		T24	66		T25	1
all_pins[22]	4215177	1			T23	1		T24	66		T25	1
all_pins[23]	4215177	1			T23	1		T24	66		T25	1
all_pins[24]	4215177	1			T23	1		T24	66		T25	1
all_pins[25]	4215177	1			T23	1		T24	66		T25	1
all_pins[26]	4215177	1			T23	1		T24	66		T25	1
all_pins[27]	4215177	1			T23	1		T24	66		T25	1
all_pins[28]	4215177	1			T23	1		T24	66		T25	1
all_pins[29]	4215177	1			T23	1		T24	66		T25	1
all_pins[30]	4215177	1			T23	1		T24	66		T25	1
all_pins[31]	4215177	1			T23	1		T24	66		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	83746299	1			T23	32		T24	1682		T25	32
values[0x1]	51139365	1			T24	430		T1	5227		T12	2212
transitions[0x0=>0x1]	30625226	1			T24	311		T1	3164		T12	1334
transitions[0x1=>0x0]	30625075	1			T24	310		T1	3163		T12	1334

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2617135	1			T23	1		T24	48		T25	1
all_pins[0]	values[0x1]	1598042	1			T24	18		T1	115		T12	82
all_pins[0]	transitions[0x0=>0x1]	988417	1			T24	6		T1	72		T12	54
all_pins[0]	transitions[0x1=>0x0]	984785	1			T24	15		T1	99		T12	28
all_pins[1]	values[0x0]	2621561	1			T23	1		T24	55		T25	1
all_pins[1]	values[0x1]	1593616	1			T24	11		T1	161		T12	56
all_pins[1]	transitions[0x0=>0x1]	952155	1			T24	7		T1	114		T12	24
all_pins[1]	transitions[0x1=>0x0]	956581	1			T24	14		T1	68		T12	50
all_pins[2]	values[0x0]	2622088	1			T23	1		T24	50		T25	1
all_pins[2]	values[0x1]	1593089	1			T24	16		T1	187		T12	104
all_pins[2]	transitions[0x0=>0x1]	955004	1			T24	9		T1	116		T12	65
all_pins[2]	transitions[0x1=>0x0]	955531	1			T24	4		T1	90		T12	17
all_pins[3]	values[0x0]	2620015	1			T23	1		T24	61		T25	1
all_pins[3]	values[0x1]	1595162	1			T24	5		T1	123		T12	77
all_pins[3]	transitions[0x0=>0x1]	955174	1			T24	5		T1	62		T12	32
all_pins[3]	transitions[0x1=>0x0]	953101	1			T24	16		T1	126		T12	59
all_pins[4]	values[0x0]	2614586	1			T23	1		T24	45		T25	1
all_pins[4]	values[0x1]	1600591	1			T24	21		T1	173		T12	36
all_pins[4]	transitions[0x0=>0x1]	958038	1			T24	19		T1	115		T12	16
all_pins[4]	transitions[0x1=>0x0]	952609	1			T24	3		T1	65		T12	57
all_pins[5]	values[0x0]	2614733	1			T23	1		T24	36		T25	1
all_pins[5]	values[0x1]	1600444	1			T24	30		T1	114		T12	81
all_pins[5]	transitions[0x0=>0x1]	958397	1			T24	14		T1	46		T12	68
all_pins[5]	transitions[0x1=>0x0]	958544	1			T24	5		T1	105		T12	23
all_pins[6]	values[0x0]	2616244	1			T23	1		T24	58		T25	1
all_pins[6]	values[0x1]	1598933	1			T24	8		T1	181		T12	87
all_pins[6]	transitions[0x0=>0x1]	959574	1			T24	1		T1	149		T12	52
all_pins[6]	transitions[0x1=>0x0]	961085	1			T24	23		T1	82		T12	46
all_pins[7]	values[0x0]	2614526	1			T23	1		T24	50		T25	1
all_pins[7]	values[0x1]	1600651	1			T24	16		T1	177		T12	68
all_pins[7]	transitions[0x0=>0x1]	955899	1			T24	13		T1	107		T12	29
all_pins[7]	transitions[0x1=>0x0]	954181	1			T24	5		T1	111		T12	48
all_pins[8]	values[0x0]	2617614	1			T23	1		T24	54		T25	1
all_pins[8]	values[0x1]	1597563	1			T24	12		T1	193		T12	72
all_pins[8]	transitions[0x0=>0x1]	954601	1			T24	5		T1	97		T12	52
all_pins[8]	transitions[0x1=>0x0]	957689	1			T24	9		T1	81		T12	48
all_pins[9]	values[0x0]	2624767	1			T23	1		T24	47		T25	1
all_pins[9]	values[0x1]	1590410	1			T24	19		T1	169		T12	66
all_pins[9]	transitions[0x0=>0x1]	952854	1			T24	12		T1	111		T12	35
all_pins[9]	transitions[0x1=>0x0]	960007	1			T24	5		T1	135		T12	41
all_pins[10]	values[0x0]	2617327	1			T23	1		T24	56		T25	1
all_pins[10]	values[0x1]	1597850	1			T24	10		T1	155		T12	68
all_pins[10]	transitions[0x0=>0x1]	960172	1			T24	9		T1	105		T12	46
all_pins[10]	transitions[0x1=>0x0]	952732	1			T24	18		T1	119		T12	44
all_pins[11]	values[0x0]	2612927	1			T23	1		T24	46		T25	1
all_pins[11]	values[0x1]	1602250	1			T24	20		T1	139		T12	40
all_pins[11]	transitions[0x0=>0x1]	958995	1			T24	12		T1	75		T12	31
all_pins[11]	transitions[0x1=>0x0]	954595	1			T24	2		T1	91		T12	59
all_pins[12]	values[0x0]	2613793	1			T23	1		T24	56		T25	1
all_pins[12]	values[0x1]	1601384	1			T24	10		T1	189		T12	64
all_pins[12]	transitions[0x0=>0x1]	953956	1			T24	9		T1	117		T12	43
all_pins[12]	transitions[0x1=>0x0]	954822	1			T24	19		T1	67		T12	19
all_pins[13]	values[0x0]	2619603	1			T23	1		T24	54		T25	1
all_pins[13]	values[0x1]	1595574	1			T24	12		T1	193		T12	71
all_pins[13]	transitions[0x0=>0x1]	952595	1			T24	10		T1	118		T12	39
all_pins[13]	transitions[0x1=>0x0]	958405	1			T24	8		T1	114		T12	32
all_pins[14]	values[0x0]	2612941	1			T23	1		T24	58		T25	1
all_pins[14]	values[0x1]	1602236	1			T24	8		T1	158		T12	77
all_pins[14]	transitions[0x0=>0x1]	957887	1			T24	4		T1	75		T12	40
all_pins[14]	transitions[0x1=>0x0]	951225	1			T24	8		T1	110		T12	34
all_pins[15]	values[0x0]	2620520	1			T23	1		T24	43		T25	1
all_pins[15]	values[0x1]	1594657	1			T24	23		T1	196		T12	92
all_pins[15]	transitions[0x0=>0x1]	952487	1			T24	23		T1	141		T12	69
all_pins[15]	transitions[0x1=>0x0]	960066	1			T24	8		T1	103		T12	54
all_pins[16]	values[0x0]	2619776	1			T23	1		T24	62		T25	1
all_pins[16]	values[0x1]	1595401	1			T24	4		T1	168		T12	97
all_pins[16]	transitions[0x0=>0x1]	955429	1			T1	81		T12	42		T14	117
all_pins[16]	transitions[0x1=>0x0]	954685	1			T24	19		T1	109		T12	37
all_pins[17]	values[0x0]	2617417	1			T23	1		T24	59		T25	1
all_pins[17]	values[0x1]	1597760	1			T24	7		T1	180		T12	60
all_pins[17]	transitions[0x0=>0x1]	956236	1			T24	7		T1	81		T12	26
all_pins[17]	transitions[0x1=>0x0]	953877	1			T24	4		T1	69		T12	63
all_pins[18]	values[0x0]	2619454	1			T23	1		T24	50		T25	1
all_pins[18]	values[0x1]	1595723	1			T24	16		T1	168		T12	46
all_pins[18]	transitions[0x0=>0x1]	954697	1			T24	15		T1	93		T12	34
all_pins[18]	transitions[0x1=>0x0]	956734	1			T24	6		T1	105		T12	48
all_pins[19]	values[0x0]	2615341	1			T23	1		T24	48		T25	1
all_pins[19]	values[0x1]	1599836	1			T24	18		T1	147		T12	72
all_pins[19]	transitions[0x0=>0x1]	958315	1			T24	14		T1	86		T12	44
all_pins[19]	transitions[0x1=>0x0]	954202	1			T24	12		T1	107		T12	18
all_pins[20]	values[0x0]	2617183	1			T23	1		T24	60		T25	1
all_pins[20]	values[0x1]	1597994	1			T24	6		T1	175		T12	83
all_pins[20]	transitions[0x0=>0x1]	954330	1			T24	2		T1	114		T12	43
all_pins[20]	transitions[0x1=>0x0]	956172	1			T24	14		T1	86		T12	32
all_pins[21]	values[0x0]	2618204	1			T23	1		T24	54		T25	1
all_pins[21]	values[0x1]	1596973	1			T24	12		T1	186		T12	75
all_pins[21]	transitions[0x0=>0x1]	953447	1			T24	11		T1	122		T12	51
all_pins[21]	transitions[0x1=>0x0]	954468	1			T24	5		T1	111		T12	59
all_pins[22]	values[0x0]	2617554	1			T23	1		T24	46		T25	1
all_pins[22]	values[0x1]	1597623	1			T24	20		T1	159		T12	63
all_pins[22]	transitions[0x0=>0x1]	955675	1			T24	19		T1	90		T12	30
all_pins[22]	transitions[0x1=>0x0]	955025	1			T24	11		T1	117		T12	42
all_pins[23]	values[0x0]	2611931	1			T23	1		T24	57		T25	1
all_pins[23]	values[0x1]	1603246	1			T24	9		T1	178		T12	53
all_pins[23]	transitions[0x0=>0x1]	960038	1			T24	5		T1	117		T12	38
all_pins[23]	transitions[0x1=>0x0]	954415	1			T24	16		T1	98		T12	48
all_pins[24]	values[0x0]	2614278	1			T23	1		T24	60		T25	1
all_pins[24]	values[0x1]	1600899	1			T24	6		T1	140		T12	66
all_pins[24]	transitions[0x0=>0x1]	954054	1			T24	6		T1	91		T12	38
all_pins[24]	transitions[0x1=>0x0]	956401	1			T24	9		T1	129		T12	25
all_pins[25]	values[0x0]	2612640	1			T23	1		T24	51		T25	1
all_pins[25]	values[0x1]	1602537	1			T24	15		T1	132		T12	59
all_pins[25]	transitions[0x0=>0x1]	959065	1			T24	15		T1	99		T12	39
all_pins[25]	transitions[0x1=>0x0]	957427	1			T24	6		T1	107		T12	46
all_pins[26]	values[0x0]	2614633	1			T23	1		T24	63		T25	1
all_pins[26]	values[0x1]	1600544	1			T24	3		T1	165		T12	71
all_pins[26]	transitions[0x0=>0x1]	954899	1			T24	3		T1	130		T12	50
all_pins[26]	transitions[0x1=>0x0]	956892	1			T24	15		T1	97		T12	38
all_pins[27]	values[0x0]	2617133	1			T23	1		T24	58		T25	1
all_pins[27]	values[0x1]	1598044	1			T24	8		T1	167		T12	85
all_pins[27]	transitions[0x0=>0x1]	955682	1			T24	8		T1	82		T12	54
all_pins[27]	transitions[0x1=>0x0]	958182	1			T24	3		T1	80		T12	40
all_pins[28]	values[0x0]	2618247	1			T23	1		T24	49		T25	1
all_pins[28]	values[0x1]	1596930	1			T24	17		T1	151		T12	45
all_pins[28]	transitions[0x0=>0x1]	954404	1			T24	13		T1	62		T12	29
all_pins[28]	transitions[0x1=>0x0]	955518	1			T24	4		T1	78		T12	69
all_pins[29]	values[0x0]	2614080	1			T23	1		T24	57		T25	1
all_pins[29]	values[0x1]	1601097	1			T24	9		T1	137		T12	58
all_pins[29]	transitions[0x0=>0x1]	959587	1			T24	4		T1	101		T12	49
all_pins[29]	transitions[0x1=>0x0]	955420	1			T24	12		T1	115		T12	36
all_pins[30]	values[0x0]	2617432	1			T23	1		T24	53		T25	1
all_pins[30]	values[0x1]	1597745	1			T24	13		T1	208		T12	82
all_pins[30]	transitions[0x0=>0x1]	955615	1			T24	13		T1	116		T12	46
all_pins[30]	transitions[0x1=>0x0]	958967	1			T24	9		T1	45		T12	22
all_pins[31]	values[0x0]	2620616	1			T23	1		T24	38		T25	1
all_pins[31]	values[0x1]	1594561	1			T24	28		T1	143		T12	56
all_pins[31]	transitions[0x0=>0x1]	957548	1			T24	18		T1	79		T12	26
all_pins[31]	transitions[0x1=>0x0]	960732	1			T24	3		T1	144		T12	52