Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14120968	1			T23	254		T24	93		T25	110
all_values[1]	14120968	1			T23	254		T24	93		T25	110
all_values[2]	14120968	1			T23	254		T24	93		T25	110
all_values[3]	14120968	1			T23	254		T24	93		T25	110
all_values[4]	14120968	1			T23	254		T24	93		T25	110
all_values[5]	14120968	1			T23	254		T24	93		T25	110
all_values[6]	14120968	1			T23	254		T24	93		T25	110
all_values[7]	14120968	1			T23	254		T24	93		T25	110
all_values[8]	14120968	1			T23	254		T24	93		T25	110
all_values[9]	14120968	1			T23	254		T24	93		T25	110
all_values[10]	14120968	1			T23	254		T24	93		T25	110
all_values[11]	14120968	1			T23	254		T24	93		T25	110
all_values[12]	14120968	1			T23	254		T24	93		T25	110
all_values[13]	14120968	1			T23	254		T24	93		T25	110
all_values[14]	14120968	1			T23	254		T24	93		T25	110
all_values[15]	14120968	1			T23	254		T24	93		T25	110
all_values[16]	14120968	1			T23	254		T24	93		T25	110
all_values[17]	14120968	1			T23	254		T24	93		T25	110
all_values[18]	14120968	1			T23	254		T24	93		T25	110
all_values[19]	14120968	1			T23	254		T24	93		T25	110
all_values[20]	14120968	1			T23	254		T24	93		T25	110
all_values[21]	14120968	1			T23	254		T24	93		T25	110
all_values[22]	14120968	1			T23	254		T24	93		T25	110
all_values[23]	14120968	1			T23	254		T24	93		T25	110
all_values[24]	14120968	1			T23	254		T24	93		T25	110
all_values[25]	14120968	1			T23	254		T24	93		T25	110
all_values[26]	14120968	1			T23	254		T24	93		T25	110
all_values[27]	14120968	1			T23	254		T24	93		T25	110
all_values[28]	14120968	1			T23	254		T24	93		T25	110
all_values[29]	14120968	1			T23	254		T24	93		T25	110
all_values[30]	14120968	1			T23	254		T24	93		T25	110
all_values[31]	14120968	1			T23	254		T24	93		T25	110

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

260616427

1

T23

8128

T24

1891

T25

3520

auto[1]

191254549

1

T24

1085

T1

18025

T12

5179

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106186187

1

T23

8128

T24

1810

T25

3520

auto[1]

345684789

1

T24

1166

T1

31714

T12

8911

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

446917523

1

T23

8128

T24

2836

T25

3520

auto[1]

4953453

1

T24

140

T1

1499

T17

1718

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2745333	1			T23	254		T24	33		T25	110
all_values[0]	auto[0]	auto[0]	auto[1]	5330103	1			T24	25		T1	554		T12	91
all_values[0]	auto[0]	auto[1]	auto[0]	581671	1			T24	13		T1	85		T12	22
all_values[0]	auto[0]	auto[1]	auto[1]	5308940	1			T24	17		T1	298		T12	178
all_values[0]	auto[1]	auto[0]	auto[1]	77811	1			T24	3		T1	26		T17	35
all_values[0]	auto[1]	auto[1]	auto[1]	77110	1			T24	2		T1	19		T17	19
all_values[1]	auto[0]	auto[0]	auto[0]	2743853	1			T23	254		T24	38		T25	110
all_values[1]	auto[0]	auto[0]	auto[1]	5345012	1			T24	28		T1	499		T12	156
all_values[1]	auto[0]	auto[1]	auto[0]	576542	1			T24	13		T1	48		T12	13
all_values[1]	auto[0]	auto[1]	auto[1]	5301060	1			T24	8		T1	436		T12	116
all_values[1]	auto[1]	auto[0]	auto[1]	77681	1			T24	4		T1	22		T17	33
all_values[1]	auto[1]	auto[1]	auto[1]	76820	1			T24	2		T1	21		T17	25
all_values[2]	auto[0]	auto[0]	auto[0]	2744786	1			T23	254		T24	36		T25	110
all_values[2]	auto[0]	auto[0]	auto[1]	5331508	1			T24	30		T1	454		T12	62
all_values[2]	auto[0]	auto[1]	auto[0]	580660	1			T24	5		T1	71		T12	33
all_values[2]	auto[0]	auto[1]	auto[1]	5309309	1			T24	17		T1	505		T12	218
all_values[2]	auto[1]	auto[0]	auto[1]	77857	1			T24	5		T1	20		T17	32
all_values[2]	auto[1]	auto[1]	auto[1]	76848	1			T1	25		T17	28		T18	1140
all_values[3]	auto[0]	auto[0]	auto[0]	2740196	1			T23	254		T24	46		T25	110
all_values[3]	auto[0]	auto[0]	auto[1]	5324349	1			T24	28		T1	581		T12	118
all_values[3]	auto[0]	auto[1]	auto[0]	582640	1			T24	10		T1	75		T12	36
all_values[3]	auto[0]	auto[1]	auto[1]	5319038	1			T24	5		T1	329		T12	150
all_values[3]	auto[1]	auto[0]	auto[1]	77884	1			T24	3		T1	32		T17	21
all_values[3]	auto[1]	auto[1]	auto[1]	76861	1			T24	1		T1	17		T17	31
all_values[4]	auto[0]	auto[0]	auto[0]	2739705	1			T23	254		T24	39		T25	110
all_values[4]	auto[0]	auto[0]	auto[1]	5359208	1			T24	18		T1	495		T12	176
all_values[4]	auto[0]	auto[1]	auto[0]	575984	1			T24	11		T1	60		T12	25
all_values[4]	auto[0]	auto[1]	auto[1]	5290880	1			T24	22		T1	491		T12	74
all_values[4]	auto[1]	auto[0]	auto[1]	77994	1			T24	2		T1	20		T17	27
all_values[4]	auto[1]	auto[1]	auto[1]	77197	1			T24	1		T1	25		T17	26
all_values[5]	auto[0]	auto[0]	auto[0]	2731132	1			T23	254		T24	29		T25	110
all_values[5]	auto[0]	auto[0]	auto[1]	5315211	1			T24	13		T1	570		T12	114
all_values[5]	auto[0]	auto[1]	auto[0]	577602	1			T24	14		T1	96		T12	27
all_values[5]	auto[0]	auto[1]	auto[1]	5342577	1			T24	37		T1	341		T12	162
all_values[5]	auto[1]	auto[0]	auto[1]	77327	1			T1	30		T17	28		T18	1189
all_values[5]	auto[1]	auto[1]	auto[1]	77119	1			T1	16		T17	23		T18	1152
all_values[6]	auto[0]	auto[0]	auto[0]	2747714	1			T23	254		T24	45		T25	110
all_values[6]	auto[0]	auto[0]	auto[1]	5320816	1			T24	14		T1	434		T12	88
all_values[6]	auto[0]	auto[1]	auto[0]	575172	1			T24	21		T1	83		T12	34
all_values[6]	auto[0]	auto[1]	auto[1]	5322404	1			T24	7		T1	553		T12	174
all_values[6]	auto[1]	auto[0]	auto[1]	77395	1			T24	4		T1	26		T17	30
all_values[6]	auto[1]	auto[1]	auto[1]	77467	1			T24	2		T1	29		T17	29
all_values[7]	auto[0]	auto[0]	auto[0]	2734447	1			T23	254		T24	34		T25	110
all_values[7]	auto[0]	auto[0]	auto[1]	5332192	1			T24	12		T1	423		T12	198
all_values[7]	auto[0]	auto[1]	auto[0]	573540	1			T24	23		T1	65		T12	6
all_values[7]	auto[0]	auto[1]	auto[1]	5325841	1			T24	19		T1	547		T12	110
all_values[7]	auto[1]	auto[0]	auto[1]	77504	1			T24	2		T1	22		T17	14
all_values[7]	auto[1]	auto[1]	auto[1]	77444	1			T24	3		T1	27		T17	32
all_values[8]	auto[0]	auto[0]	auto[0]	2742077	1			T23	254		T24	42		T25	110
all_values[8]	auto[0]	auto[0]	auto[1]	5327321	1			T1	366		T12	154		T14	696
all_values[8]	auto[0]	auto[1]	auto[0]	579312	1			T24	35		T1	115		T12	23
all_values[8]	auto[0]	auto[1]	auto[1]	5317143	1			T24	11		T1	553		T12	134
all_values[8]	auto[1]	auto[0]	auto[1]	77131	1			T24	2		T1	22		T17	32
all_values[8]	auto[1]	auto[1]	auto[1]	77984	1			T24	3		T1	35		T17	18
all_values[9]	auto[0]	auto[0]	auto[0]	2740734	1			T23	254		T24	35		T25	110
all_values[9]	auto[0]	auto[0]	auto[1]	5363393	1			T24	18		T1	379		T12	138
all_values[9]	auto[0]	auto[1]	auto[0]	582812	1			T24	15		T1	59		T12	29
all_values[9]	auto[0]	auto[1]	auto[1]	5279248	1			T24	19		T1	566		T12	144
all_values[9]	auto[1]	auto[0]	auto[1]	77809	1			T24	4		T1	21		T17	32
all_values[9]	auto[1]	auto[1]	auto[1]	76972	1			T24	2		T1	23		T17	22
all_values[10]	auto[0]	auto[0]	auto[0]	2742519	1			T23	254		T24	37		T25	110
all_values[10]	auto[0]	auto[0]	auto[1]	5328833	1			T24	4		T1	555		T12	145
all_values[10]	auto[0]	auto[1]	auto[0]	576657	1			T24	41		T1	19		T12	21
all_values[10]	auto[0]	auto[1]	auto[1]	5317849	1			T24	8		T1	437		T12	136
all_values[10]	auto[1]	auto[0]	auto[1]	78053	1			T1	18		T17	22		T18	1262
all_values[10]	auto[1]	auto[1]	auto[1]	77057	1			T24	3		T1	25		T17	30
all_values[11]	auto[0]	auto[0]	auto[0]	2734130	1			T23	254		T24	32		T25	110
all_values[11]	auto[0]	auto[0]	auto[1]	5329698	1			T24	19		T1	528		T12	177
all_values[11]	auto[0]	auto[1]	auto[0]	578635	1			T24	18		T1	76		T12	30
all_values[11]	auto[0]	auto[1]	auto[1]	5323738	1			T24	19		T1	378		T12	101
all_values[11]	auto[1]	auto[0]	auto[1]	77422	1			T24	3		T1	23		T17	36
all_values[11]	auto[1]	auto[1]	auto[1]	77345	1			T24	2		T1	29		T17	24
all_values[12]	auto[0]	auto[0]	auto[0]	2735678	1			T23	254		T24	40		T25	110
all_values[12]	auto[0]	auto[0]	auto[1]	5335507	1			T24	23		T1	541		T12	151
all_values[12]	auto[0]	auto[1]	auto[0]	577899	1			T24	18		T1	34		T12	8
all_values[12]	auto[0]	auto[1]	auto[1]	5316810	1			T24	11		T1	466		T12	136
all_values[12]	auto[1]	auto[0]	auto[1]	77886	1			T24	1		T1	18		T17	29
all_values[12]	auto[1]	auto[1]	auto[1]	77188	1			T1	21		T17	25		T18	1192
all_values[13]	auto[0]	auto[0]	auto[0]	2741756	1			T23	254		T24	32		T25	110
all_values[13]	auto[0]	auto[0]	auto[1]	5303158	1			T24	32		T1	436		T12	136
all_values[13]	auto[0]	auto[1]	auto[0]	571133	1			T24	12		T1	64		T12	42
all_values[13]	auto[0]	auto[1]	auto[1]	5350370	1			T24	11		T1	509		T12	135
all_values[13]	auto[1]	auto[0]	auto[1]	77210	1			T24	5		T1	25		T17	25
all_values[13]	auto[1]	auto[1]	auto[1]	77341	1			T24	1		T1	25		T17	27
all_values[14]	auto[0]	auto[0]	auto[0]	2740477	1			T23	254		T24	59		T25	110
all_values[14]	auto[0]	auto[0]	auto[1]	5329112	1			T24	15		T1	493		T12	101
all_values[14]	auto[0]	auto[1]	auto[0]	581022	1			T24	11		T1	96		T12	30
all_values[14]	auto[0]	auto[1]	auto[1]	5315901	1			T24	6		T1	415		T12	163
all_values[14]	auto[1]	auto[0]	auto[1]	77255	1			T24	2		T1	24		T17	33
all_values[14]	auto[1]	auto[1]	auto[1]	77201	1			T1	19		T17	19		T18	1228
all_values[15]	auto[0]	auto[0]	auto[0]	2745573	1			T23	254		T24	36		T25	110
all_values[15]	auto[0]	auto[0]	auto[1]	5336755	1			T24	9		T1	411		T12	105
all_values[15]	auto[0]	auto[1]	auto[0]	573960	1			T24	17		T1	73		T12	16
all_values[15]	auto[0]	auto[1]	auto[1]	5309719	1			T24	26		T1	499		T12	182
all_values[15]	auto[1]	auto[0]	auto[1]	77653	1			T24	1		T1	15		T17	31
all_values[15]	auto[1]	auto[1]	auto[1]	77308	1			T24	4		T1	31		T17	20
all_values[16]	auto[0]	auto[0]	auto[0]	2755449	1			T23	254		T24	45		T25	110
all_values[16]	auto[0]	auto[0]	auto[1]	5323656	1			T24	11		T1	530		T12	111
all_values[16]	auto[0]	auto[1]	auto[0]	579827	1			T24	27		T1	45		T12	10
all_values[16]	auto[0]	auto[1]	auto[1]	5307081	1			T24	6		T1	459		T12	199
all_values[16]	auto[1]	auto[0]	auto[1]	78157	1			T24	4		T1	27		T17	14
all_values[16]	auto[1]	auto[1]	auto[1]	76798	1			T1	25		T17	38		T18	1199
all_values[17]	auto[0]	auto[0]	auto[0]	2735522	1			T23	254		T24	42		T25	110
all_values[17]	auto[0]	auto[0]	auto[1]	5333633	1			T24	16		T1	422		T12	143
all_values[17]	auto[0]	auto[1]	auto[0]	573722	1			T24	27		T1	62		T12	33
all_values[17]	auto[0]	auto[1]	auto[1]	5323327	1			T24	5		T1	554		T12	133
all_values[17]	auto[1]	auto[0]	auto[1]	77581	1			T24	1		T1	28		T17	23
all_values[17]	auto[1]	auto[1]	auto[1]	77183	1			T24	2		T1	24		T17	35
all_values[18]	auto[0]	auto[0]	auto[0]	2733973	1			T23	254		T24	29		T25	110
all_values[18]	auto[0]	auto[0]	auto[1]	5333540	1			T24	18		T1	523		T12	171
all_values[18]	auto[0]	auto[1]	auto[0]	577544	1			T24	24		T1	71		T12	13
all_values[18]	auto[0]	auto[1]	auto[1]	5321125	1			T24	17		T1	436		T12	94
all_values[18]	auto[1]	auto[0]	auto[1]	77433	1			T24	2		T1	27		T17	28
all_values[18]	auto[1]	auto[1]	auto[1]	77353	1			T24	3		T1	14		T17	29
all_values[19]	auto[0]	auto[0]	auto[0]	2737592	1			T23	254		T24	27		T25	110
all_values[19]	auto[0]	auto[0]	auto[1]	5321163	1			T24	10		T1	415		T12	126
all_values[19]	auto[0]	auto[1]	auto[0]	580202	1			T24	29		T1	100		T12	42
all_values[19]	auto[0]	auto[1]	auto[1]	5326944	1			T24	22		T1	507		T12	143
all_values[19]	auto[1]	auto[0]	auto[1]	78078	1			T24	2		T1	25		T17	33
all_values[19]	auto[1]	auto[1]	auto[1]	76989	1			T24	3		T1	22		T17	16
all_values[20]	auto[0]	auto[0]	auto[0]	2741018	1			T23	254		T24	49		T25	110
all_values[20]	auto[0]	auto[0]	auto[1]	5323474	1			T24	21		T1	478		T12	120
all_values[20]	auto[0]	auto[1]	auto[0]	579505	1			T24	12		T1	61		T12	14
all_values[20]	auto[0]	auto[1]	auto[1]	5322241	1			T24	7		T1	489		T12	166
all_values[20]	auto[1]	auto[0]	auto[1]	77714	1			T24	4		T1	17		T17	31
all_values[20]	auto[1]	auto[1]	auto[1]	77016	1			T1	25		T17	22		T18	1097
all_values[21]	auto[0]	auto[0]	auto[0]	2734516	1			T23	254		T24	37		T25	110
all_values[21]	auto[0]	auto[0]	auto[1]	5326575	1			T24	21		T1	339		T12	137
all_values[21]	auto[0]	auto[1]	auto[0]	583701	1			T24	15		T1	86		T12	28
all_values[21]	auto[0]	auto[1]	auto[1]	5321301	1			T24	16		T1	633		T12	152
all_values[21]	auto[1]	auto[0]	auto[1]	77780	1			T24	2		T1	25		T17	23
all_values[21]	auto[1]	auto[1]	auto[1]	77095	1			T24	2		T1	23		T17	39
all_values[22]	auto[0]	auto[0]	auto[0]	2736802	1			T23	254		T24	32		T25	110
all_values[22]	auto[0]	auto[0]	auto[1]	5301941	1			T24	26		T1	560		T12	128
all_values[22]	auto[0]	auto[1]	auto[0]	581538	1			T24	11		T1	47		T12	42
all_values[22]	auto[0]	auto[1]	auto[1]	5345957	1			T24	21		T1	397		T12	119
all_values[22]	auto[1]	auto[0]	auto[1]	77423	1			T24	2		T1	23		T17	32
all_values[22]	auto[1]	auto[1]	auto[1]	77307	1			T24	1		T1	22		T17	26
all_values[23]	auto[0]	auto[0]	auto[0]	2740011	1			T23	254		T24	31		T25	110
all_values[23]	auto[0]	auto[0]	auto[1]	5274421	1			T24	30		T1	382		T12	188
all_values[23]	auto[0]	auto[1]	auto[0]	592439	1			T24	15		T1	84		T12	17
all_values[23]	auto[0]	auto[1]	auto[1]	5359411	1			T24	11		T1	589		T12	106
all_values[23]	auto[1]	auto[0]	auto[1]	77344	1			T24	5		T1	20		T17	32
all_values[23]	auto[1]	auto[1]	auto[1]	77342	1			T24	1		T1	24		T17	22
all_values[24]	auto[0]	auto[0]	auto[0]	2739410	1			T23	254		T24	40		T25	110
all_values[24]	auto[0]	auto[0]	auto[1]	5313643	1			T24	16		T1	443		T12	148
all_values[24]	auto[0]	auto[1]	auto[0]	579326	1			T24	26		T1	55		T12	22
all_values[24]	auto[0]	auto[1]	auto[1]	5333660	1			T24	4		T1	479		T12	143
all_values[24]	auto[1]	auto[0]	auto[1]	77826	1			T24	6		T1	26		T17	18
all_values[24]	auto[1]	auto[1]	auto[1]	77103	1			T24	1		T1	23		T17	30
all_values[25]	auto[0]	auto[0]	auto[0]	2737037	1			T23	254		T24	42		T25	110
all_values[25]	auto[0]	auto[0]	auto[1]	5336469	1			T24	3		T1	584		T12	174
all_values[25]	auto[0]	auto[1]	auto[0]	574061	1			T24	29		T1	60		T12	20
all_values[25]	auto[0]	auto[1]	auto[1]	5318358	1			T24	15		T1	353		T12	99
all_values[25]	auto[1]	auto[0]	auto[1]	77599	1			T24	1		T1	32		T17	23
all_values[25]	auto[1]	auto[1]	auto[1]	77444	1			T24	3		T1	17		T17	29
all_values[26]	auto[0]	auto[0]	auto[0]	2747181	1			T23	254		T24	30		T25	110
all_values[26]	auto[0]	auto[0]	auto[1]	5314496	1			T24	35		T1	359		T12	154
all_values[26]	auto[0]	auto[1]	auto[0]	575299	1			T24	18		T1	106		T12	28
all_values[26]	auto[0]	auto[1]	auto[1]	5329484	1			T24	4		T1	544		T12	122
all_values[26]	auto[1]	auto[0]	auto[1]	77183	1			T24	6		T1	25		T17	22
all_values[26]	auto[1]	auto[1]	auto[1]	77325	1			T1	20		T17	20		T18	1213
all_values[27]	auto[0]	auto[0]	auto[0]	2739406	1			T23	254		T24	41		T25	110
all_values[27]	auto[0]	auto[0]	auto[1]	5328031	1			T24	19		T1	425		T12	127
all_values[27]	auto[0]	auto[1]	auto[0]	575146	1			T24	24		T1	101		T12	18
all_values[27]	auto[0]	auto[1]	auto[1]	5323678	1			T24	6		T1	472		T12	172
all_values[27]	auto[1]	auto[0]	auto[1]	77172	1			T24	2		T1	16		T17	32
all_values[27]	auto[1]	auto[1]	auto[1]	77535	1			T24	1		T1	34		T17	18
all_values[28]	auto[0]	auto[0]	auto[0]	2736239	1			T23	254		T24	44		T25	110
all_values[28]	auto[0]	auto[0]	auto[1]	5302600	1			T24	12		T1	461		T12	220
all_values[28]	auto[0]	auto[1]	auto[0]	582236	1			T24	13		T1	95		T12	8
all_values[28]	auto[0]	auto[1]	auto[1]	5345242	1			T24	20		T1	508		T12	76
all_values[28]	auto[1]	auto[0]	auto[1]	77951	1			T24	3		T1	29		T17	39
all_values[28]	auto[1]	auto[1]	auto[1]	76700	1			T24	1		T1	19		T17	18
all_values[29]	auto[0]	auto[0]	auto[0]	2732876	1			T23	254		T24	44		T25	110
all_values[29]	auto[0]	auto[0]	auto[1]	5340697	1			T24	21		T1	584		T12	129
all_values[29]	auto[0]	auto[1]	auto[0]	577483	1			T24	13		T1	49		T12	33
all_values[29]	auto[0]	auto[1]	auto[1]	5314736	1			T24	11		T1	384		T12	130
all_values[29]	auto[1]	auto[0]	auto[1]	77835	1			T24	4		T1	30		T17	30
all_values[29]	auto[1]	auto[1]	auto[1]	77341	1			T1	9		T17	23		T18	1145
all_values[30]	auto[0]	auto[0]	auto[0]	2739497	1			T23	254		T24	47		T25	110
all_values[30]	auto[0]	auto[0]	auto[1]	5336248	1			T24	14		T1	430		T12	141
all_values[30]	auto[0]	auto[1]	auto[0]	570977	1			T24	11		T1	33		T12	16
all_values[30]	auto[0]	auto[1]	auto[1]	5319804	1			T24	15		T1	534		T12	150
all_values[30]	auto[1]	auto[0]	auto[1]	77673	1			T24	5		T1	19		T17	40
all_values[30]	auto[1]	auto[1]	auto[1]	76769	1			T24	1		T1	25		T17	21
all_values[31]	auto[0]	auto[0]	auto[0]	2741481	1			T23	254		T24	32		T25	110
all_values[31]	auto[0]	auto[0]	auto[1]	5331760	1			T24	12		T1	513		T12	169
all_values[31]	auto[0]	auto[1]	auto[0]	579820	1			T24	14		T1	65		T12	25
all_values[31]	auto[0]	auto[1]	auto[1]	5313637	1			T24	30		T1	387		T12	98
all_values[31]	auto[1]	auto[0]	auto[1]	77163	1			T24	3		T1	28		T17	25
all_values[31]	auto[1]	auto[1]	auto[1]	77107	1			T24	2		T1	25		T17	29

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal