Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[1]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[2]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[3]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[4]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[5]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[6]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[7]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[8]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[9]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[10]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[11]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[12]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[13]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[14]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[15]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[16]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[17]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[18]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[19]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[20]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[21]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[22]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[23]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[24]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[25]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[26]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[27]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[28]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[29]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[30]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[31]	13920383	1			T23	470		T24	114		T25	205

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265647208

1

T23

3869

T24

2181

T25

5284

auto[1]

179805048

1

T23

11171

T24

1467

T25

1276

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357262654

1

T23

8271

T24

3321

T25

6197

auto[1]

88189602

1

T23

6769

T24

327

T25

363

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331209967

1

T23

8016

T24

2721

T25

4086

auto[1]

114242289

1

T23

7024

T24

927

T25

2474

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5166272	1			T23	18		T24	34		T25	111
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3800698	1			T23	109		T24	46		T25	24
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1386439	1			T23	107		T24	5		T25	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1750957	1			T24	4		T25	53		T1	21
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	440226	1			T23	122		T24	6		T25	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1375791	1			T23	114		T24	19		T1	177
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5155080	1			T23	18		T24	41		T25	78
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3802769	1			T23	139		T24	34		T25	27
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1383617	1			T23	126		T24	5		T25	3
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1760243	1			T24	28		T25	75		T1	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	440997	1			T23	97		T24	3		T25	20
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1377677	1			T23	90		T24	3		T25	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5160328	1			T23	16		T24	44		T25	90
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3813409	1			T23	157		T24	16		T25	20
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1384071	1			T23	126		T24	7		T25	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1751261	1			T24	18		T25	70		T1	11
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	438800	1			T23	97		T24	4		T25	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1372514	1			T23	74		T24	25		T25	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5157510	1			T23	17		T24	53		T25	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3808338	1			T23	140		T24	19		T25	16
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1388713	1			T23	97		T24	3		T25	8
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1749436	1			T24	26		T25	107		T1	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	439417	1			T23	108		T24	6		T25	18
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1376969	1			T23	108		T24	7		T25	10
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5167116	1			T23	15		T24	36		T25	84
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3802083	1			T23	160		T24	46		T25	12
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1390677	1			T23	87		T25	3		T1	246
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1748432	1			T24	4		T25	75		T1	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	440278	1			T23	118		T24	3		T25	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1371797	1			T23	90		T24	25		T25	10
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5155848	1			T23	18		T24	22		T25	92
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3809701	1			T23	113		T24	42		T25	38
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1384480	1			T23	92		T25	1		T1	225
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1755314	1			T24	18		T25	69		T1	21
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	442692	1			T23	130		T24	16		T25	5
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1372348	1			T23	117		T24	16		T1	250
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5161383	1			T23	21		T24	68		T25	111
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3804478	1			T23	146		T24	10		T25	30
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1389941	1			T23	92		T24	3		T25	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1752905	1			T24	33		T25	40		T1	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	440776	1			T23	111		T25	13		T1	280
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1370900	1			T23	100		T1	183		T15	92
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5161208	1			T23	13		T24	46		T25	141
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3800193	1			T23	160		T24	16		T25	31
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1384744	1			T23	97		T24	3		T25	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1756361	1			T24	23		T25	23		T1	22
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	442857	1			T23	96		T24	11		T25	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1375020	1			T23	104		T24	15		T1	151
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5164807	1			T23	18		T24	49		T25	80
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3804837	1			T23	141		T24	30		T25	20
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1388402	1			T23	103		T24	13		T25	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1748482	1			T24	16		T25	74		T1	18
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	438100	1			T23	102		T24	3		T25	23
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1375755	1			T23	106		T24	3		T25	6
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5166740	1			T23	21		T24	60		T25	62
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3798855	1			T23	118		T24	8		T25	9
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1382971	1			T23	100		T24	3		T25	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1759121	1			T24	26		T25	101		T1	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	444027	1			T23	130		T24	3		T25	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1368669	1			T23	101		T24	14		T25	12
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5168003	1			T23	20		T24	67		T25	97
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3802728	1			T23	151		T24	7		T25	30
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1388447	1			T23	119		T24	4		T25	3
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1748129	1			T24	27		T25	62		T1	22
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	437812	1			T23	86		T24	4		T25	7
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1375264	1			T23	94		T24	5		T25	6
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5158466	1			T23	12		T24	66		T25	119
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3805800	1			T23	135		T24	23		T25	24
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1385765	1			T23	100		T25	15		T1	267
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1756131	1			T24	12		T25	35		T1	26
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	439987	1			T23	98		T24	2		T25	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1374234	1			T23	125		T24	11		T25	2
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5142258	1			T23	22		T24	35		T25	131
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3815130	1			T23	81		T24	49		T25	34
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1385361	1			T23	135		T24	4		T25	9
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1760412	1			T24	13		T25	21		T1	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	442734	1			T23	94		T24	5		T25	8
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1374488	1			T23	138		T24	8		T25	2
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5153931	1			T23	20		T24	52		T25	110
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3811541	1			T23	125		T24	24		T25	33
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1380611	1			T23	109		T24	2		T25	7
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1757352	1			T24	18		T25	37		T1	30
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	441844	1			T23	124		T24	5		T25	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1375104	1			T23	92		T24	13		T25	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5156117	1			T23	20		T24	30		T25	103
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3804670	1			T23	118		T24	39		T25	26
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1384864	1			T23	124		T25	4		T1	139
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1755741	1			T24	30		T25	55		T1	31
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	440610	1			T23	112		T24	11		T25	11
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1378381	1			T23	96		T24	4		T25	6
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5165062	1			T23	20		T24	75		T25	89
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3800602	1			T23	137		T24	20		T25	23
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1392228	1			T23	113		T24	7		T25	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1745551	1			T24	5		T25	62		T1	23
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	443135	1			T23	80		T24	2		T25	14
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1373805	1			T23	120		T24	5		T25	11
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5160757	1			T23	16		T24	71		T25	84
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3808427	1			T23	119		T24	21		T25	10
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1378792	1			T23	139		T24	2		T25	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1756973	1			T24	10		T25	90		T1	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	441127	1			T23	78		T24	1		T25	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1374307	1			T23	118		T24	9		T25	6
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5165767	1			T23	13		T24	50		T25	109
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3809923	1			T23	134		T24	49		T25	22
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1384440	1			T23	99		T25	15		T1	266
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1756991	1			T24	6		T25	41		T1	14
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	439645	1			T23	130		T24	6		T25	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1363617	1			T23	94		T24	3		T25	8
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5165864	1			T23	16		T24	52		T25	64
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3801031	1			T23	125		T24	24		T25	13
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1378777	1			T23	90		T24	5		T25	5
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1760245	1			T24	22		T25	94		T1	25
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	443341	1			T23	125		T24	8		T25	23
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1371125	1			T23	114		T24	3		T25	6
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5162203	1			T23	18		T24	27		T25	134
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3807449	1			T23	125		T24	60		T25	23
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1380545	1			T23	84		T24	4		T25	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1757649	1			T24	12		T25	38		T1	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	443774	1			T23	111		T24	8		T25	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1368763	1			T23	132		T24	3		T1	215
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5157832	1			T23	15		T24	40		T25	94
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3808647	1			T23	140		T24	54		T25	17
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1380922	1			T23	111		T24	2		T25	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1760605	1			T24	14		T25	66		T1	14
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	445510	1			T23	98		T24	2		T25	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1366867	1			T23	106		T24	2		T25	6
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5174217	1			T23	18		T24	62		T25	83
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3795116	1			T23	107		T24	16		T25	28
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1378820	1			T23	109		T24	4		T25	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1761294	1			T24	31		T25	66		T1	21
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	443003	1			T23	124		T25	15		T1	311
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1367933	1			T23	112		T24	1		T25	8
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5168075	1			T23	20		T24	59		T25	110
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3803632	1			T23	105		T24	37		T25	31
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1379662	1			T23	94		T24	1		T25	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1760175	1			T24	10		T25	34		T1	10
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	442297	1			T23	140		T24	6		T25	9
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1366542	1			T23	111		T24	1		T25	10
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5155031	1			T23	18		T24	56		T25	97
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3812873	1			T23	149		T24	16		T25	21
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1383875	1			T23	91		T25	9		T1	190
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1756610	1			T24	13		T25	56		T1	23
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	441980	1			T23	110		T24	21		T25	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1370014	1			T23	102		T24	8		T25	6
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5154894	1			T23	15		T24	68		T25	139
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3807886	1			T23	150		T24	36		T25	27
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1378292	1			T23	90		T24	2		T25	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1760553	1			T24	7		T25	24		T1	34
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	442889	1			T23	104		T25	5		T1	403
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1375869	1			T23	111		T24	1		T25	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5158020	1			T23	18		T24	50		T25	84
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3808573	1			T23	142		T24	39		T25	19
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1379682	1			T23	106		T24	1		T25	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1762621	1			T24	13		T25	77		T1	38
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	442695	1			T23	110		T24	7		T25	10
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1368792	1			T23	94		T24	4		T25	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5157294	1			T23	24		T24	36		T25	79
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3808905	1			T23	116		T24	45		T25	22
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1384532	1			T23	122		T24	2		T25	5
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1756745	1			T24	22		T25	73		T1	21
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	441291	1			T23	106		T24	6		T25	18
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1371616	1			T23	102		T24	3		T25	8
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5163602	1			T23	20		T24	33		T25	60
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3800249	1			T23	110		T24	55		T25	16
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1381845	1			T23	80		T25	2		T1	277
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1760859	1			T24	13		T25	103		T1	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	442700	1			T23	144		T24	11		T25	20
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1371128	1			T23	116		T24	2		T25	4
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5167486	1			T23	14		T24	27		T25	112
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3797216	1			T23	128		T24	69		T25	16
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1381699	1			T23	84		T25	2		T1	212
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1759256	1			T24	17		T25	66		T1	21
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	442231	1			T23	124		T25	9		T1	338
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1372495	1			T23	120		T24	1		T1	224
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5169470	1			T23	16		T24	64		T25	107
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3801620	1			T23	131		T24	28		T25	23
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1382677	1			T23	80		T25	5		T1	175
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1757795	1			T24	5		T25	60		T1	24
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	440309	1			T23	138		T24	1		T25	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1368512	1			T23	105		T24	16		T25	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5156711	1			T23	15		T24	64		T25	134
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3805835	1			T23	116		T24	20		T25	25
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1379217	1			T23	116		T24	4		T25	10
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1762512	1			T24	12		T25	30		T1	23
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	442284	1			T23	114		T24	5		T25	4
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1373824	1			T23	109		T24	9		T25	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5171383	1			T23	18		T24	46		T25	106
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3799535	1			T23	120		T24	54		T25	22
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1383375	1			T23	84		T25	10		T1	214
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1753279	1			T24	4		T25	53		T1	19
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	441812	1			T23	100		T24	8		T25	12
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1370999	1			T23	148		T24	2		T25	2

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal