Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[1]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[2]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[3]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[4]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[5]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[6]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[7]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[8]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[9]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[10]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[11]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[12]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[13]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[14]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[15]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[16]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[17]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[18]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[19]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[20]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[21]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[22]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[23]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[24]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[25]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[26]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[27]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[28]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[29]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[30]	13920383	1			T23	470		T24	114		T25	205
bins_for_gpio_bits[31]	13920383	1			T23	470		T24	114		T25	205

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265647208

1

T23

3869

T24

2181

T25

5284

auto[1]

179805048

1

T23

11171

T24

1467

T25

1276

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265638923

1

T23

3883

T24

2168

T25

5284

auto[1]

179813333

1

T23

11157

T24

1480

T25

1276

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8057661	1			T23	97		T24	43		T25	175
bins_for_gpio_bits[0]	auto[0]	auto[1]	245754	1			T23	29		T1	25		T15	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	246007	1			T23	28		T1	25		T15	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	5370961	1			T23	316		T24	71		T25	30
bins_for_gpio_bits[1]	auto[0]	auto[0]	8052247	1			T23	118		T24	73		T25	155
bins_for_gpio_bits[1]	auto[0]	auto[1]	246475	1			T23	26		T25	1		T1	33
bins_for_gpio_bits[1]	auto[1]	auto[0]	246693	1			T23	26		T24	1		T25	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5374968	1			T23	300		T24	40		T25	48
bins_for_gpio_bits[2]	auto[0]	auto[0]	8049921	1			T23	115		T24	68		T25	173
bins_for_gpio_bits[2]	auto[0]	auto[1]	245500	1			T23	27		T24	1		T25	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	245739	1			T23	27		T24	1		T25	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5379223	1			T23	301		T24	44		T25	30
bins_for_gpio_bits[3]	auto[0]	auto[0]	8049296	1			T23	88		T24	80		T25	156
bins_for_gpio_bits[3]	auto[0]	auto[1]	246071	1			T23	27		T24	1		T25	5
bins_for_gpio_bits[3]	auto[1]	auto[0]	246363	1			T23	26		T24	2		T25	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	5378653	1			T23	329		T24	31		T25	39
bins_for_gpio_bits[4]	auto[0]	auto[0]	8060636	1			T23	79		T24	39		T25	159
bins_for_gpio_bits[4]	auto[0]	auto[1]	245317	1			T23	24		T25	3		T1	36
bins_for_gpio_bits[4]	auto[1]	auto[0]	245589	1			T23	23		T24	1		T25	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	5368841	1			T23	344		T24	74		T25	40
bins_for_gpio_bits[5]	auto[0]	auto[0]	8049019	1			T23	82		T24	39		T25	162
bins_for_gpio_bits[5]	auto[0]	auto[1]	246344	1			T23	28		T1	32		T13	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	246623	1			T23	28		T24	1		T1	32
bins_for_gpio_bits[5]	auto[1]	auto[1]	5378397	1			T23	332		T24	74		T25	43
bins_for_gpio_bits[6]	auto[0]	auto[0]	8058456	1			T23	82		T24	104		T25	162
bins_for_gpio_bits[6]	auto[0]	auto[1]	245521	1			T23	31		T1	28		T15	16
bins_for_gpio_bits[6]	auto[1]	auto[0]	245773	1			T23	31		T1	28		T15	16
bins_for_gpio_bits[6]	auto[1]	auto[1]	5370633	1			T23	326		T24	10		T25	43
bins_for_gpio_bits[7]	auto[0]	auto[0]	8056152	1			T23	84		T24	72		T25	170
bins_for_gpio_bits[7]	auto[0]	auto[1]	245851	1			T23	27		T1	25		T15	10
bins_for_gpio_bits[7]	auto[1]	auto[0]	246161	1			T23	26		T1	25		T15	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	5372219	1			T23	333		T24	42		T25	35
bins_for_gpio_bits[8]	auto[0]	auto[0]	8055456	1			T23	93		T24	77		T25	153
bins_for_gpio_bits[8]	auto[0]	auto[1]	246023	1			T23	29		T25	3		T1	29
bins_for_gpio_bits[8]	auto[1]	auto[0]	246235	1			T23	28		T24	1		T25	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	5372669	1			T23	320		T24	36		T25	46
bins_for_gpio_bits[9]	auto[0]	auto[0]	8062863	1			T23	98		T24	89		T25	162
bins_for_gpio_bits[9]	auto[0]	auto[1]	245675	1			T23	23		T25	4		T1	25
bins_for_gpio_bits[9]	auto[1]	auto[0]	245969	1			T23	23		T25	4		T1	25
bins_for_gpio_bits[9]	auto[1]	auto[1]	5365876	1			T23	326		T24	25		T25	35
bins_for_gpio_bits[10]	auto[0]	auto[0]	8057970	1			T23	113		T24	97		T25	159
bins_for_gpio_bits[10]	auto[0]	auto[1]	246326	1			T23	27		T25	3		T1	24
bins_for_gpio_bits[10]	auto[1]	auto[0]	246609	1			T23	26		T24	1		T25	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	5369478	1			T23	304		T24	16		T25	40
bins_for_gpio_bits[11]	auto[0]	auto[0]	8053778	1			T23	87		T24	77		T25	168
bins_for_gpio_bits[11]	auto[0]	auto[1]	246306	1			T23	25		T24	1		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	246584	1			T23	25		T24	1		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5373715	1			T23	333		T24	35		T25	35
bins_for_gpio_bits[12]	auto[0]	auto[0]	8041375	1			T23	132		T24	50		T25	160
bins_for_gpio_bits[12]	auto[0]	auto[1]	246407	1			T23	26		T24	1		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	246656	1			T23	25		T24	2		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	5385945	1			T23	287		T24	61		T25	43
bins_for_gpio_bits[13]	auto[0]	auto[0]	8045774	1			T23	101		T24	72		T25	153
bins_for_gpio_bits[13]	auto[0]	auto[1]	245865	1			T23	29		T25	1		T1	26
bins_for_gpio_bits[13]	auto[1]	auto[0]	246120	1			T23	28		T25	1		T1	26
bins_for_gpio_bits[13]	auto[1]	auto[1]	5382624	1			T23	312		T24	42		T25	50
bins_for_gpio_bits[14]	auto[0]	auto[0]	8049777	1			T23	112		T24	59		T25	159
bins_for_gpio_bits[14]	auto[0]	auto[1]	246700	1			T23	32		T24	1		T25	3
bins_for_gpio_bits[14]	auto[1]	auto[0]	246945	1			T23	32		T24	1		T25	3
bins_for_gpio_bits[14]	auto[1]	auto[1]	5376961	1			T23	294		T24	53		T25	40
bins_for_gpio_bits[15]	auto[0]	auto[0]	8056622	1			T23	105		T24	87		T25	152
bins_for_gpio_bits[15]	auto[0]	auto[1]	245987	1			T23	29		T24	1		T25	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	246219	1			T23	28		T25	5		T1	28
bins_for_gpio_bits[15]	auto[1]	auto[1]	5371555	1			T23	308		T24	26		T25	43
bins_for_gpio_bits[16]	auto[0]	auto[0]	8050017	1			T23	124		T24	83		T25	176
bins_for_gpio_bits[16]	auto[0]	auto[1]	246256	1			T23	32		T25	1		T1	37
bins_for_gpio_bits[16]	auto[1]	auto[0]	246505	1			T23	31		T25	1		T1	37
bins_for_gpio_bits[16]	auto[1]	auto[1]	5377605	1			T23	283		T24	31		T25	27
bins_for_gpio_bits[17]	auto[0]	auto[0]	8061032	1			T23	89		T24	55		T25	161
bins_for_gpio_bits[17]	auto[0]	auto[1]	245937	1			T23	24		T25	4		T1	33
bins_for_gpio_bits[17]	auto[1]	auto[0]	246166	1			T23	23		T24	1		T25	4
bins_for_gpio_bits[17]	auto[1]	auto[1]	5367248	1			T23	334		T24	58		T25	36
bins_for_gpio_bits[18]	auto[0]	auto[0]	8057976	1			T23	83		T24	79		T25	160
bins_for_gpio_bits[18]	auto[0]	auto[1]	246656	1			T23	23		T25	3		T1	33
bins_for_gpio_bits[18]	auto[1]	auto[0]	246910	1			T23	23		T25	3		T1	33
bins_for_gpio_bits[18]	auto[1]	auto[1]	5368841	1			T23	341		T24	35		T25	39
bins_for_gpio_bits[19]	auto[0]	auto[0]	8054472	1			T23	79		T24	42		T25	175
bins_for_gpio_bits[19]	auto[0]	auto[1]	245656	1			T23	23		T1	38		T15	17
bins_for_gpio_bits[19]	auto[1]	auto[0]	245925	1			T23	23		T24	1		T1	38
bins_for_gpio_bits[19]	auto[1]	auto[1]	5374330	1			T23	345		T24	71		T25	30
bins_for_gpio_bits[20]	auto[0]	auto[0]	8053975	1			T23	101		T24	55		T25	164
bins_for_gpio_bits[20]	auto[0]	auto[1]	245128	1			T23	26		T25	2		T1	33
bins_for_gpio_bits[20]	auto[1]	auto[0]	245384	1			T23	25		T24	1		T25	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	5375896	1			T23	318		T24	58		T25	37
bins_for_gpio_bits[21]	auto[0]	auto[0]	8068407	1			T23	104		T24	96		T25	150
bins_for_gpio_bits[21]	auto[0]	auto[1]	245682	1			T23	24		T25	4		T1	36
bins_for_gpio_bits[21]	auto[1]	auto[0]	245924	1			T23	23		T24	1		T25	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	5360370	1			T23	319		T24	17		T25	47
bins_for_gpio_bits[22]	auto[0]	auto[0]	8061767	1			T23	90		T24	70		T25	153
bins_for_gpio_bits[22]	auto[0]	auto[1]	245878	1			T23	24		T25	2		T1	34
bins_for_gpio_bits[22]	auto[1]	auto[0]	246145	1			T23	24		T25	2		T1	34
bins_for_gpio_bits[22]	auto[1]	auto[1]	5366593	1			T23	332		T24	44		T25	48
bins_for_gpio_bits[23]	auto[0]	auto[0]	8049042	1			T23	81		T24	69		T25	160
bins_for_gpio_bits[23]	auto[0]	auto[1]	246200	1			T23	29		T25	2		T1	31
bins_for_gpio_bits[23]	auto[1]	auto[0]	246474	1			T23	28		T25	2		T1	31
bins_for_gpio_bits[23]	auto[1]	auto[1]	5378667	1			T23	332		T24	45		T25	41
bins_for_gpio_bits[24]	auto[0]	auto[0]	8046955	1			T23	80		T24	76		T25	167
bins_for_gpio_bits[24]	auto[0]	auto[1]	246553	1			T23	25		T25	2		T1	33
bins_for_gpio_bits[24]	auto[1]	auto[0]	246784	1			T23	25		T24	1		T25	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	5380091	1			T23	340		T24	37		T25	34
bins_for_gpio_bits[25]	auto[0]	auto[0]	8055033	1			T23	98		T24	64		T25	170
bins_for_gpio_bits[25]	auto[0]	auto[1]	245014	1			T23	26		T25	2		T1	29
bins_for_gpio_bits[25]	auto[1]	auto[0]	245290	1			T23	26		T25	2		T1	28
bins_for_gpio_bits[25]	auto[1]	auto[1]	5375046	1			T23	320		T24	50		T25	31
bins_for_gpio_bits[26]	auto[0]	auto[0]	8052187	1			T23	117		T24	59		T25	154
bins_for_gpio_bits[26]	auto[0]	auto[1]	246115	1			T23	29		T25	3		T1	28
bins_for_gpio_bits[26]	auto[1]	auto[0]	246384	1			T23	29		T24	1		T25	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	5375697	1			T23	295		T24	54		T25	45
bins_for_gpio_bits[27]	auto[0]	auto[0]	8060178	1			T23	74		T24	46		T25	163
bins_for_gpio_bits[27]	auto[0]	auto[1]	245884	1			T23	26		T25	2		T1	37
bins_for_gpio_bits[27]	auto[1]	auto[0]	246128	1			T23	26		T25	2		T1	36
bins_for_gpio_bits[27]	auto[1]	auto[1]	5368193	1			T23	344		T24	68		T25	38
bins_for_gpio_bits[28]	auto[0]	auto[0]	8061956	1			T23	73		T24	43		T25	180
bins_for_gpio_bits[28]	auto[0]	auto[1]	246216	1			T23	25		T1	34		T15	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	246485	1			T23	25		T24	1		T1	34
bins_for_gpio_bits[28]	auto[1]	auto[1]	5365726	1			T23	347		T24	70		T25	25
bins_for_gpio_bits[29]	auto[0]	auto[0]	8063632	1			T23	74		T24	69		T25	171
bins_for_gpio_bits[29]	auto[0]	auto[1]	246053	1			T23	22		T25	1		T1	29
bins_for_gpio_bits[29]	auto[1]	auto[0]	246310	1			T23	22		T25	1		T1	29
bins_for_gpio_bits[29]	auto[1]	auto[1]	5364388	1			T23	352		T24	45		T25	32
bins_for_gpio_bits[30]	auto[0]	auto[0]	8051597	1			T23	107		T24	79		T25	173
bins_for_gpio_bits[30]	auto[0]	auto[1]	246568	1			T23	24		T24	1		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	246843	1			T23	24		T24	1		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5375375	1			T23	315		T24	33		T25	30
bins_for_gpio_bits[31]	auto[0]	auto[0]	8062032	1			T23	74		T24	50		T25	168
bins_for_gpio_bits[31]	auto[0]	auto[1]	245744	1			T23	28		T25	1		T1	29
bins_for_gpio_bits[31]	auto[1]	auto[0]	246005	1			T23	28		T25	1		T1	29
bins_for_gpio_bits[31]	auto[1]	auto[1]	5366602	1			T23	340		T24	64		T25	35