Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8153247 |
1 |
|
|
T23 |
254 |
|
T24 |
61 |
|
T25 |
110 |
| auto[1] |
5967721 |
1 |
|
|
T24 |
32 |
|
T1 |
402 |
|
T12 |
200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356260 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
764708 |
1 |
|
|
T1 |
19 |
|
T12 |
9 |
|
T14 |
126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136370 |
1 |
|
|
T23 |
254 |
|
T24 |
70 |
|
T25 |
110 |
| auto[1] |
5984598 |
1 |
|
|
T24 |
23 |
|
T1 |
504 |
|
T12 |
179 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2605375 |
1 |
|
|
T24 |
13 |
|
T1 |
296 |
|
T12 |
69 |
| auto[1] |
auto[0] |
auto[1] |
381800 |
1 |
|
|
T1 |
13 |
|
T12 |
4 |
|
T14 |
57 |
| auto[1] |
auto[1] |
auto[0] |
2614515 |
1 |
|
|
T24 |
10 |
|
T1 |
189 |
|
T12 |
101 |
| auto[1] |
auto[1] |
auto[1] |
382908 |
1 |
|
|
T1 |
6 |
|
T12 |
5 |
|
T14 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166546 |
1 |
|
|
T23 |
254 |
|
T24 |
70 |
|
T25 |
110 |
| auto[1] |
5954422 |
1 |
|
|
T24 |
23 |
|
T1 |
505 |
|
T12 |
129 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13355359 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
765609 |
1 |
|
|
T1 |
33 |
|
T12 |
5 |
|
T14 |
127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8137857 |
1 |
|
|
T23 |
254 |
|
T24 |
59 |
|
T25 |
110 |
| auto[1] |
5983111 |
1 |
|
|
T24 |
34 |
|
T1 |
578 |
|
T12 |
108 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2618488 |
1 |
|
|
T24 |
22 |
|
T1 |
301 |
|
T12 |
67 |
| auto[1] |
auto[0] |
auto[1] |
385499 |
1 |
|
|
T1 |
25 |
|
T12 |
4 |
|
T14 |
67 |
| auto[1] |
auto[1] |
auto[0] |
2599014 |
1 |
|
|
T24 |
12 |
|
T1 |
244 |
|
T12 |
36 |
| auto[1] |
auto[1] |
auto[1] |
380110 |
1 |
|
|
T1 |
8 |
|
T12 |
1 |
|
T14 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8149405 |
1 |
|
|
T23 |
254 |
|
T24 |
41 |
|
T25 |
110 |
| auto[1] |
5971563 |
1 |
|
|
T24 |
52 |
|
T1 |
481 |
|
T12 |
157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13355216 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
765752 |
1 |
|
|
T1 |
20 |
|
T12 |
9 |
|
T14 |
156 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8131150 |
1 |
|
|
T23 |
254 |
|
T24 |
63 |
|
T25 |
110 |
| auto[1] |
5989818 |
1 |
|
|
T24 |
30 |
|
T1 |
582 |
|
T12 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2612062 |
1 |
|
|
T24 |
7 |
|
T1 |
328 |
|
T12 |
77 |
| auto[1] |
auto[0] |
auto[1] |
381813 |
1 |
|
|
T1 |
12 |
|
T12 |
5 |
|
T14 |
87 |
| auto[1] |
auto[1] |
auto[0] |
2612004 |
1 |
|
|
T24 |
23 |
|
T1 |
234 |
|
T12 |
59 |
| auto[1] |
auto[1] |
auto[1] |
383939 |
1 |
|
|
T1 |
8 |
|
T12 |
4 |
|
T14 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8141250 |
1 |
|
|
T23 |
254 |
|
T24 |
54 |
|
T25 |
110 |
| auto[1] |
5979718 |
1 |
|
|
T24 |
39 |
|
T1 |
483 |
|
T12 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356672 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
764296 |
1 |
|
|
T24 |
1 |
|
T1 |
26 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8149706 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5971262 |
1 |
|
|
T24 |
33 |
|
T1 |
462 |
|
T12 |
106 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2601394 |
1 |
|
|
T24 |
20 |
|
T1 |
243 |
|
T12 |
68 |
| auto[1] |
auto[0] |
auto[1] |
381876 |
1 |
|
|
T24 |
1 |
|
T1 |
16 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2605572 |
1 |
|
|
T24 |
12 |
|
T1 |
193 |
|
T12 |
33 |
| auto[1] |
auto[1] |
auto[1] |
382420 |
1 |
|
|
T1 |
10 |
|
T12 |
2 |
|
T14 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8149071 |
1 |
|
|
T23 |
254 |
|
T24 |
64 |
|
T25 |
110 |
| auto[1] |
5971897 |
1 |
|
|
T24 |
29 |
|
T1 |
521 |
|
T12 |
144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13359625 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
761343 |
1 |
|
|
T1 |
28 |
|
T12 |
15 |
|
T14 |
132 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166180 |
1 |
|
|
T23 |
254 |
|
T24 |
57 |
|
T25 |
110 |
| auto[1] |
5954788 |
1 |
|
|
T24 |
36 |
|
T1 |
552 |
|
T12 |
222 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2604766 |
1 |
|
|
T24 |
21 |
|
T1 |
270 |
|
T12 |
113 |
| auto[1] |
auto[0] |
auto[1] |
381781 |
1 |
|
|
T1 |
14 |
|
T12 |
8 |
|
T14 |
68 |
| auto[1] |
auto[1] |
auto[0] |
2588679 |
1 |
|
|
T24 |
15 |
|
T1 |
254 |
|
T12 |
94 |
| auto[1] |
auto[1] |
auto[1] |
379562 |
1 |
|
|
T1 |
14 |
|
T12 |
7 |
|
T14 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8122124 |
1 |
|
|
T23 |
254 |
|
T24 |
69 |
|
T25 |
110 |
| auto[1] |
5998844 |
1 |
|
|
T24 |
24 |
|
T1 |
598 |
|
T12 |
177 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356832 |
1 |
|
|
T23 |
254 |
|
T24 |
91 |
|
T25 |
110 |
| auto[1] |
764136 |
1 |
|
|
T24 |
2 |
|
T1 |
24 |
|
T12 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8135836 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5985132 |
1 |
|
|
T24 |
33 |
|
T1 |
567 |
|
T12 |
154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2593214 |
1 |
|
|
T24 |
18 |
|
T1 |
252 |
|
T12 |
70 |
| auto[1] |
auto[0] |
auto[1] |
379228 |
1 |
|
|
T24 |
1 |
|
T1 |
13 |
|
T12 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2627782 |
1 |
|
|
T24 |
13 |
|
T1 |
291 |
|
T12 |
74 |
| auto[1] |
auto[1] |
auto[1] |
384908 |
1 |
|
|
T24 |
1 |
|
T1 |
11 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146844 |
1 |
|
|
T23 |
254 |
|
T24 |
76 |
|
T25 |
110 |
| auto[1] |
5974124 |
1 |
|
|
T24 |
17 |
|
T1 |
530 |
|
T12 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13362099 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
758869 |
1 |
|
|
T1 |
27 |
|
T12 |
10 |
|
T14 |
105 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8176341 |
1 |
|
|
T23 |
254 |
|
T24 |
67 |
|
T25 |
110 |
| auto[1] |
5944627 |
1 |
|
|
T24 |
26 |
|
T1 |
638 |
|
T12 |
173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2591223 |
1 |
|
|
T24 |
22 |
|
T1 |
303 |
|
T12 |
64 |
| auto[1] |
auto[0] |
auto[1] |
378280 |
1 |
|
|
T1 |
12 |
|
T12 |
5 |
|
T14 |
45 |
| auto[1] |
auto[1] |
auto[0] |
2594535 |
1 |
|
|
T24 |
4 |
|
T1 |
308 |
|
T12 |
99 |
| auto[1] |
auto[1] |
auto[1] |
380589 |
1 |
|
|
T1 |
15 |
|
T12 |
5 |
|
T14 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8159981 |
1 |
|
|
T23 |
254 |
|
T24 |
46 |
|
T25 |
110 |
| auto[1] |
5960987 |
1 |
|
|
T24 |
47 |
|
T1 |
603 |
|
T12 |
198 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13354823 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
766145 |
1 |
|
|
T24 |
1 |
|
T1 |
29 |
|
T12 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8135194 |
1 |
|
|
T23 |
254 |
|
T24 |
64 |
|
T25 |
110 |
| auto[1] |
5985774 |
1 |
|
|
T24 |
29 |
|
T1 |
588 |
|
T12 |
143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614881 |
1 |
|
|
T24 |
19 |
|
T1 |
248 |
|
T12 |
43 |
| auto[1] |
auto[0] |
auto[1] |
384059 |
1 |
|
|
T24 |
1 |
|
T1 |
11 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2604748 |
1 |
|
|
T24 |
9 |
|
T1 |
311 |
|
T12 |
89 |
| auto[1] |
auto[1] |
auto[1] |
382086 |
1 |
|
|
T1 |
18 |
|
T12 |
7 |
|
T14 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8157262 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5963706 |
1 |
|
|
T24 |
33 |
|
T1 |
529 |
|
T12 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356344 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
764624 |
1 |
|
|
T1 |
29 |
|
T12 |
9 |
|
T14 |
135 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136890 |
1 |
|
|
T23 |
254 |
|
T24 |
65 |
|
T25 |
110 |
| auto[1] |
5984078 |
1 |
|
|
T24 |
28 |
|
T1 |
639 |
|
T12 |
128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2603198 |
1 |
|
|
T24 |
16 |
|
T1 |
289 |
|
T12 |
34 |
| auto[1] |
auto[0] |
auto[1] |
381192 |
1 |
|
|
T1 |
15 |
|
T12 |
2 |
|
T14 |
91 |
| auto[1] |
auto[1] |
auto[0] |
2616256 |
1 |
|
|
T24 |
12 |
|
T1 |
321 |
|
T12 |
85 |
| auto[1] |
auto[1] |
auto[1] |
383432 |
1 |
|
|
T1 |
14 |
|
T12 |
7 |
|
T14 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146736 |
1 |
|
|
T23 |
254 |
|
T24 |
59 |
|
T25 |
110 |
| auto[1] |
5974232 |
1 |
|
|
T24 |
34 |
|
T1 |
640 |
|
T12 |
166 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13354870 |
1 |
|
|
T23 |
254 |
|
T24 |
91 |
|
T25 |
110 |
| auto[1] |
766098 |
1 |
|
|
T24 |
2 |
|
T1 |
26 |
|
T12 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8137221 |
1 |
|
|
T23 |
254 |
|
T24 |
52 |
|
T25 |
110 |
| auto[1] |
5983747 |
1 |
|
|
T24 |
41 |
|
T1 |
545 |
|
T12 |
155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2608864 |
1 |
|
|
T24 |
23 |
|
T1 |
252 |
|
T12 |
77 |
| auto[1] |
auto[0] |
auto[1] |
382813 |
1 |
|
|
T24 |
1 |
|
T1 |
13 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2608785 |
1 |
|
|
T24 |
16 |
|
T1 |
267 |
|
T12 |
70 |
| auto[1] |
auto[1] |
auto[1] |
383285 |
1 |
|
|
T24 |
1 |
|
T1 |
13 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8144946 |
1 |
|
|
T23 |
254 |
|
T24 |
49 |
|
T25 |
110 |
| auto[1] |
5976022 |
1 |
|
|
T24 |
44 |
|
T1 |
521 |
|
T12 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356664 |
1 |
|
|
T23 |
254 |
|
T24 |
91 |
|
T25 |
110 |
| auto[1] |
764304 |
1 |
|
|
T24 |
2 |
|
T1 |
31 |
|
T12 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8142573 |
1 |
|
|
T23 |
254 |
|
T24 |
50 |
|
T25 |
110 |
| auto[1] |
5978395 |
1 |
|
|
T24 |
43 |
|
T1 |
605 |
|
T12 |
193 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2622399 |
1 |
|
|
T24 |
11 |
|
T1 |
305 |
|
T12 |
108 |
| auto[1] |
auto[0] |
auto[1] |
385472 |
1 |
|
|
T24 |
1 |
|
T1 |
16 |
|
T12 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2591692 |
1 |
|
|
T24 |
30 |
|
T1 |
269 |
|
T12 |
69 |
| auto[1] |
auto[1] |
auto[1] |
378832 |
1 |
|
|
T24 |
1 |
|
T1 |
15 |
|
T12 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136833 |
1 |
|
|
T23 |
254 |
|
T24 |
39 |
|
T25 |
110 |
| auto[1] |
5984135 |
1 |
|
|
T24 |
54 |
|
T1 |
629 |
|
T12 |
185 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356390 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
764578 |
1 |
|
|
T1 |
30 |
|
T12 |
10 |
|
T14 |
185 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8135790 |
1 |
|
|
T23 |
254 |
|
T24 |
64 |
|
T25 |
110 |
| auto[1] |
5985178 |
1 |
|
|
T24 |
29 |
|
T1 |
568 |
|
T12 |
159 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2599662 |
1 |
|
|
T24 |
15 |
|
T1 |
203 |
|
T12 |
79 |
| auto[1] |
auto[0] |
auto[1] |
379484 |
1 |
|
|
T1 |
6 |
|
T12 |
7 |
|
T14 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2620938 |
1 |
|
|
T24 |
14 |
|
T1 |
335 |
|
T12 |
70 |
| auto[1] |
auto[1] |
auto[1] |
385094 |
1 |
|
|
T1 |
24 |
|
T12 |
3 |
|
T14 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8154151 |
1 |
|
|
T23 |
254 |
|
T24 |
71 |
|
T25 |
110 |
| auto[1] |
5966817 |
1 |
|
|
T24 |
22 |
|
T1 |
601 |
|
T12 |
251 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13352458 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
768510 |
1 |
|
|
T24 |
1 |
|
T1 |
24 |
|
T12 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8105520 |
1 |
|
|
T23 |
254 |
|
T24 |
70 |
|
T25 |
110 |
| auto[1] |
6015448 |
1 |
|
|
T24 |
23 |
|
T1 |
466 |
|
T12 |
164 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2615982 |
1 |
|
|
T24 |
14 |
|
T1 |
272 |
|
T12 |
30 |
| auto[1] |
auto[0] |
auto[1] |
382314 |
1 |
|
|
T24 |
1 |
|
T1 |
17 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2630956 |
1 |
|
|
T24 |
8 |
|
T1 |
170 |
|
T12 |
124 |
| auto[1] |
auto[1] |
auto[1] |
386196 |
1 |
|
|
T1 |
7 |
|
T12 |
9 |
|
T14 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8142206 |
1 |
|
|
T23 |
254 |
|
T24 |
74 |
|
T25 |
110 |
| auto[1] |
5978762 |
1 |
|
|
T24 |
19 |
|
T1 |
575 |
|
T12 |
180 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13360919 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
760049 |
1 |
|
|
T1 |
20 |
|
T12 |
12 |
|
T14 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166970 |
1 |
|
|
T23 |
254 |
|
T24 |
75 |
|
T25 |
110 |
| auto[1] |
5953998 |
1 |
|
|
T24 |
18 |
|
T1 |
473 |
|
T12 |
163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2598238 |
1 |
|
|
T24 |
18 |
|
T1 |
272 |
|
T12 |
60 |
| auto[1] |
auto[0] |
auto[1] |
380383 |
1 |
|
|
T1 |
13 |
|
T12 |
6 |
|
T14 |
81 |
| auto[1] |
auto[1] |
auto[0] |
2595711 |
1 |
|
|
T1 |
181 |
|
T12 |
91 |
|
T14 |
197 |
| auto[1] |
auto[1] |
auto[1] |
379666 |
1 |
|
|
T1 |
7 |
|
T12 |
6 |
|
T14 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138871 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5982097 |
1 |
|
|
T24 |
33 |
|
T1 |
742 |
|
T12 |
180 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13359388 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
761580 |
1 |
|
|
T24 |
1 |
|
T1 |
25 |
|
T12 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8156591 |
1 |
|
|
T23 |
254 |
|
T24 |
73 |
|
T25 |
110 |
| auto[1] |
5964377 |
1 |
|
|
T24 |
20 |
|
T1 |
538 |
|
T12 |
199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2605159 |
1 |
|
|
T24 |
9 |
|
T1 |
161 |
|
T12 |
84 |
| auto[1] |
auto[0] |
auto[1] |
381255 |
1 |
|
|
T24 |
1 |
|
T1 |
8 |
|
T12 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2597638 |
1 |
|
|
T24 |
10 |
|
T1 |
352 |
|
T12 |
99 |
| auto[1] |
auto[1] |
auto[1] |
380325 |
1 |
|
|
T1 |
17 |
|
T12 |
8 |
|
T14 |
86 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8116166 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
6004802 |
1 |
|
|
T24 |
33 |
|
T1 |
466 |
|
T12 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13358877 |
1 |
|
|
T23 |
254 |
|
T24 |
91 |
|
T25 |
110 |
| auto[1] |
762091 |
1 |
|
|
T24 |
2 |
|
T1 |
25 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8161604 |
1 |
|
|
T23 |
254 |
|
T24 |
78 |
|
T25 |
110 |
| auto[1] |
5959364 |
1 |
|
|
T24 |
15 |
|
T1 |
641 |
|
T12 |
91 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2585453 |
1 |
|
|
T24 |
6 |
|
T1 |
366 |
|
T12 |
49 |
| auto[1] |
auto[0] |
auto[1] |
378592 |
1 |
|
|
T24 |
1 |
|
T1 |
18 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2611820 |
1 |
|
|
T24 |
7 |
|
T1 |
250 |
|
T12 |
38 |
| auto[1] |
auto[1] |
auto[1] |
383499 |
1 |
|
|
T24 |
1 |
|
T1 |
7 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8091776 |
1 |
|
|
T23 |
254 |
|
T24 |
66 |
|
T25 |
110 |
| auto[1] |
6029192 |
1 |
|
|
T24 |
27 |
|
T1 |
697 |
|
T12 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13362526 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
758442 |
1 |
|
|
T24 |
1 |
|
T1 |
28 |
|
T12 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173391 |
1 |
|
|
T23 |
254 |
|
T24 |
75 |
|
T25 |
110 |
| auto[1] |
5947577 |
1 |
|
|
T24 |
18 |
|
T1 |
598 |
|
T12 |
190 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2574679 |
1 |
|
|
T24 |
10 |
|
T1 |
209 |
|
T12 |
98 |
| auto[1] |
auto[0] |
auto[1] |
374695 |
1 |
|
|
T24 |
1 |
|
T1 |
10 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2614456 |
1 |
|
|
T24 |
7 |
|
T1 |
361 |
|
T12 |
78 |
| auto[1] |
auto[1] |
auto[1] |
383747 |
1 |
|
|
T1 |
18 |
|
T12 |
7 |
|
T14 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8130879 |
1 |
|
|
T23 |
254 |
|
T24 |
62 |
|
T25 |
110 |
| auto[1] |
5990089 |
1 |
|
|
T24 |
31 |
|
T1 |
557 |
|
T12 |
165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13360547 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
760421 |
1 |
|
|
T24 |
1 |
|
T1 |
22 |
|
T12 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8162969 |
1 |
|
|
T23 |
254 |
|
T24 |
57 |
|
T25 |
110 |
| auto[1] |
5957999 |
1 |
|
|
T24 |
36 |
|
T1 |
603 |
|
T12 |
163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2596351 |
1 |
|
|
T24 |
22 |
|
T1 |
333 |
|
T12 |
59 |
| auto[1] |
auto[0] |
auto[1] |
378308 |
1 |
|
|
T24 |
1 |
|
T1 |
11 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2601227 |
1 |
|
|
T24 |
13 |
|
T1 |
248 |
|
T12 |
89 |
| auto[1] |
auto[1] |
auto[1] |
382113 |
1 |
|
|
T1 |
11 |
|
T12 |
8 |
|
T14 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8151105 |
1 |
|
|
T23 |
254 |
|
T24 |
46 |
|
T25 |
110 |
| auto[1] |
5969863 |
1 |
|
|
T24 |
47 |
|
T1 |
430 |
|
T12 |
119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13361172 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
759796 |
1 |
|
|
T24 |
1 |
|
T1 |
21 |
|
T12 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8172321 |
1 |
|
|
T23 |
254 |
|
T24 |
74 |
|
T25 |
110 |
| auto[1] |
5948647 |
1 |
|
|
T24 |
19 |
|
T1 |
497 |
|
T12 |
128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2593668 |
1 |
|
|
T1 |
271 |
|
T12 |
78 |
|
T14 |
371 |
| auto[1] |
auto[0] |
auto[1] |
379532 |
1 |
|
|
T1 |
13 |
|
T12 |
5 |
|
T14 |
92 |
| auto[1] |
auto[1] |
auto[0] |
2595183 |
1 |
|
|
T24 |
18 |
|
T1 |
205 |
|
T12 |
44 |
| auto[1] |
auto[1] |
auto[1] |
380264 |
1 |
|
|
T24 |
1 |
|
T1 |
8 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138860 |
1 |
|
|
T23 |
254 |
|
T24 |
71 |
|
T25 |
110 |
| auto[1] |
5982108 |
1 |
|
|
T24 |
22 |
|
T1 |
670 |
|
T12 |
150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13360867 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
760101 |
1 |
|
|
T24 |
1 |
|
T1 |
27 |
|
T12 |
10 |