Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8123670 |
1 |
|
|
T23 |
254 |
|
T24 |
42 |
|
T25 |
110 |
| auto[1] |
5997298 |
1 |
|
|
T24 |
51 |
|
T1 |
453 |
|
T12 |
189 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13354028 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
766940 |
1 |
|
|
T1 |
19 |
|
T12 |
11 |
|
T14 |
171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8123748 |
1 |
|
|
T23 |
254 |
|
T24 |
71 |
|
T25 |
110 |
| auto[1] |
5997220 |
1 |
|
|
T24 |
22 |
|
T1 |
478 |
|
T12 |
136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2621390 |
1 |
|
|
T24 |
14 |
|
T1 |
287 |
|
T12 |
65 |
| auto[1] |
auto[0] |
auto[1] |
384748 |
1 |
|
|
T1 |
13 |
|
T12 |
4 |
|
T14 |
62 |
| auto[1] |
auto[1] |
auto[0] |
2608890 |
1 |
|
|
T24 |
8 |
|
T1 |
172 |
|
T12 |
60 |
| auto[1] |
auto[1] |
auto[1] |
382192 |
1 |
|
|
T1 |
6 |
|
T12 |
7 |
|
T14 |
109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |