Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8145925 |
1 |
|
|
T23 |
254 |
|
T24 |
63 |
|
T25 |
110 |
| auto[1] |
5975043 |
1 |
|
|
T24 |
30 |
|
T1 |
665 |
|
T12 |
208 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356050 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
764918 |
1 |
|
|
T1 |
22 |
|
T12 |
18 |
|
T14 |
175 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8137749 |
1 |
|
|
T23 |
254 |
|
T24 |
63 |
|
T25 |
110 |
| auto[1] |
5983219 |
1 |
|
|
T24 |
30 |
|
T1 |
574 |
|
T12 |
238 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2612407 |
1 |
|
|
T24 |
17 |
|
T1 |
231 |
|
T12 |
81 |
| auto[1] |
auto[0] |
auto[1] |
382496 |
1 |
|
|
T1 |
11 |
|
T12 |
7 |
|
T14 |
90 |
| auto[1] |
auto[1] |
auto[0] |
2605894 |
1 |
|
|
T24 |
13 |
|
T1 |
321 |
|
T12 |
139 |
| auto[1] |
auto[1] |
auto[1] |
382422 |
1 |
|
|
T1 |
11 |
|
T12 |
11 |
|
T14 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |