Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8144143 |
1 |
|
|
T23 |
254 |
|
T24 |
48 |
|
T25 |
110 |
| auto[1] |
5976825 |
1 |
|
|
T24 |
45 |
|
T1 |
639 |
|
T12 |
116 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13354295 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
766673 |
1 |
|
|
T24 |
1 |
|
T1 |
21 |
|
T12 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8113703 |
1 |
|
|
T23 |
254 |
|
T24 |
65 |
|
T25 |
110 |
| auto[1] |
6007265 |
1 |
|
|
T24 |
28 |
|
T1 |
521 |
|
T12 |
201 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2627433 |
1 |
|
|
T24 |
11 |
|
T1 |
223 |
|
T12 |
119 |
| auto[1] |
auto[0] |
auto[1] |
383759 |
1 |
|
|
T24 |
1 |
|
T1 |
9 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2613159 |
1 |
|
|
T24 |
16 |
|
T1 |
277 |
|
T12 |
72 |
| auto[1] |
auto[1] |
auto[1] |
382914 |
1 |
|
|
T1 |
12 |
|
T12 |
4 |
|
T14 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |