Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181936 |
1 |
|
|
T23 |
254 |
|
T24 |
57 |
|
T25 |
110 |
| auto[1] |
5939032 |
1 |
|
|
T24 |
36 |
|
T1 |
648 |
|
T12 |
173 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13357455 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
763513 |
1 |
|
|
T24 |
1 |
|
T1 |
24 |
|
T12 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146724 |
1 |
|
|
T23 |
254 |
|
T24 |
66 |
|
T25 |
110 |
| auto[1] |
5974244 |
1 |
|
|
T24 |
27 |
|
T1 |
646 |
|
T12 |
153 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2630176 |
1 |
|
|
T24 |
15 |
|
T1 |
307 |
|
T12 |
70 |
| auto[1] |
auto[0] |
auto[1] |
385705 |
1 |
|
|
T1 |
9 |
|
T12 |
6 |
|
T14 |
71 |
| auto[1] |
auto[1] |
auto[0] |
2580555 |
1 |
|
|
T24 |
11 |
|
T1 |
315 |
|
T12 |
72 |
| auto[1] |
auto[1] |
auto[1] |
377808 |
1 |
|
|
T24 |
1 |
|
T1 |
15 |
|
T12 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |