Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8153247 |
1 |
|
|
T23 |
254 |
|
T24 |
61 |
|
T25 |
110 |
| auto[1] |
5967721 |
1 |
|
|
T24 |
32 |
|
T1 |
402 |
|
T12 |
200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11653851 |
1 |
|
|
T23 |
254 |
|
T24 |
58 |
|
T25 |
110 |
| auto[1] |
2467117 |
1 |
|
|
T24 |
35 |
|
T1 |
338 |
|
T12 |
106 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8153274 |
1 |
|
|
T23 |
254 |
|
T24 |
54 |
|
T25 |
110 |
| auto[1] |
5967694 |
1 |
|
|
T24 |
39 |
|
T1 |
409 |
|
T12 |
149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1758313 |
1 |
|
|
T24 |
2 |
|
T1 |
56 |
|
T12 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1233777 |
1 |
|
|
T24 |
21 |
|
T1 |
247 |
|
T12 |
41 |
| auto[1] |
auto[1] |
auto[0] |
1742264 |
1 |
|
|
T24 |
2 |
|
T1 |
15 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[1] |
1233340 |
1 |
|
|
T24 |
14 |
|
T1 |
91 |
|
T12 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |