Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166546 |
1 |
|
|
T23 |
254 |
|
T24 |
70 |
|
T25 |
110 |
| auto[1] |
5954422 |
1 |
|
|
T24 |
23 |
|
T1 |
505 |
|
T12 |
129 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11653116 |
1 |
|
|
T23 |
254 |
|
T24 |
79 |
|
T25 |
110 |
| auto[1] |
2467852 |
1 |
|
|
T24 |
14 |
|
T1 |
393 |
|
T12 |
91 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8145079 |
1 |
|
|
T23 |
254 |
|
T24 |
65 |
|
T25 |
110 |
| auto[1] |
5975889 |
1 |
|
|
T24 |
28 |
|
T1 |
566 |
|
T12 |
168 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1754949 |
1 |
|
|
T24 |
10 |
|
T1 |
94 |
|
T12 |
41 |
| auto[1] |
auto[0] |
auto[1] |
1237471 |
1 |
|
|
T24 |
12 |
|
T1 |
210 |
|
T12 |
62 |
| auto[1] |
auto[1] |
auto[0] |
1753088 |
1 |
|
|
T24 |
4 |
|
T1 |
79 |
|
T12 |
36 |
| auto[1] |
auto[1] |
auto[1] |
1230381 |
1 |
|
|
T24 |
2 |
|
T1 |
183 |
|
T12 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |