Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8149405 |
1 |
|
|
T23 |
254 |
|
T24 |
41 |
|
T25 |
110 |
| auto[1] |
5971563 |
1 |
|
|
T24 |
52 |
|
T1 |
481 |
|
T12 |
157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652342 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
2468626 |
1 |
|
|
T1 |
505 |
|
T12 |
109 |
|
T14 |
335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8141738 |
1 |
|
|
T23 |
254 |
|
T24 |
81 |
|
T25 |
110 |
| auto[1] |
5979230 |
1 |
|
|
T24 |
12 |
|
T1 |
629 |
|
T12 |
195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1754565 |
1 |
|
|
T1 |
73 |
|
T12 |
39 |
|
T14 |
147 |
| auto[1] |
auto[0] |
auto[1] |
1234757 |
1 |
|
|
T1 |
290 |
|
T12 |
30 |
|
T14 |
180 |
| auto[1] |
auto[1] |
auto[0] |
1756039 |
1 |
|
|
T24 |
12 |
|
T1 |
51 |
|
T12 |
47 |
| auto[1] |
auto[1] |
auto[1] |
1233869 |
1 |
|
|
T1 |
215 |
|
T12 |
79 |
|
T14 |
155 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |