Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8141250 |
1 |
|
|
T23 |
254 |
|
T24 |
54 |
|
T25 |
110 |
| auto[1] |
5979718 |
1 |
|
|
T24 |
39 |
|
T1 |
483 |
|
T12 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652544 |
1 |
|
|
T23 |
254 |
|
T24 |
77 |
|
T25 |
110 |
| auto[1] |
2468424 |
1 |
|
|
T24 |
16 |
|
T1 |
381 |
|
T12 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136702 |
1 |
|
|
T23 |
254 |
|
T24 |
64 |
|
T25 |
110 |
| auto[1] |
5984266 |
1 |
|
|
T24 |
29 |
|
T1 |
559 |
|
T12 |
130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1754901 |
1 |
|
|
T24 |
13 |
|
T1 |
107 |
|
T12 |
35 |
| auto[1] |
auto[0] |
auto[1] |
1231524 |
1 |
|
|
T24 |
2 |
|
T1 |
206 |
|
T12 |
38 |
| auto[1] |
auto[1] |
auto[0] |
1760941 |
1 |
|
|
T1 |
71 |
|
T12 |
25 |
|
T14 |
121 |
| auto[1] |
auto[1] |
auto[1] |
1236900 |
1 |
|
|
T24 |
14 |
|
T1 |
175 |
|
T12 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |