Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8149071 |
1 |
|
|
T23 |
254 |
|
T24 |
64 |
|
T25 |
110 |
| auto[1] |
5971897 |
1 |
|
|
T24 |
29 |
|
T1 |
521 |
|
T12 |
144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11656899 |
1 |
|
|
T23 |
254 |
|
T24 |
74 |
|
T25 |
110 |
| auto[1] |
2464069 |
1 |
|
|
T24 |
19 |
|
T1 |
359 |
|
T12 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8150647 |
1 |
|
|
T23 |
254 |
|
T24 |
72 |
|
T25 |
110 |
| auto[1] |
5970321 |
1 |
|
|
T24 |
21 |
|
T1 |
511 |
|
T12 |
177 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1757806 |
1 |
|
|
T24 |
2 |
|
T1 |
68 |
|
T12 |
72 |
| auto[1] |
auto[0] |
auto[1] |
1234785 |
1 |
|
|
T24 |
9 |
|
T1 |
158 |
|
T12 |
38 |
| auto[1] |
auto[1] |
auto[0] |
1748446 |
1 |
|
|
T1 |
84 |
|
T12 |
30 |
|
T14 |
155 |
| auto[1] |
auto[1] |
auto[1] |
1229284 |
1 |
|
|
T24 |
10 |
|
T1 |
201 |
|
T12 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |