Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8156047 |
1 |
|
|
T23 |
254 |
|
T24 |
66 |
|
T25 |
110 |
| auto[1] |
5964921 |
1 |
|
|
T24 |
27 |
|
T1 |
620 |
|
T12 |
179 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2596757 |
1 |
|
|
T24 |
22 |
|
T1 |
211 |
|
T12 |
91 |
| auto[1] |
auto[0] |
auto[1] |
379412 |
1 |
|
|
T24 |
1 |
|
T1 |
10 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2608063 |
1 |
|
|
T24 |
4 |
|
T1 |
382 |
|
T12 |
78 |
| auto[1] |
auto[1] |
auto[1] |
380689 |
1 |
|
|
T1 |
17 |
|
T12 |
3 |
|
T14 |
84 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |