Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8122124 |
1 |
|
|
T23 |
254 |
|
T24 |
69 |
|
T25 |
110 |
| auto[1] |
5998844 |
1 |
|
|
T24 |
24 |
|
T1 |
598 |
|
T12 |
177 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11653861 |
1 |
|
|
T23 |
254 |
|
T24 |
85 |
|
T25 |
110 |
| auto[1] |
2467107 |
1 |
|
|
T24 |
8 |
|
T1 |
517 |
|
T12 |
125 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8149700 |
1 |
|
|
T23 |
254 |
|
T24 |
75 |
|
T25 |
110 |
| auto[1] |
5971268 |
1 |
|
|
T24 |
18 |
|
T1 |
596 |
|
T12 |
162 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1749443 |
1 |
|
|
T24 |
8 |
|
T1 |
48 |
|
T12 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1232984 |
1 |
|
|
T24 |
7 |
|
T1 |
208 |
|
T12 |
59 |
| auto[1] |
auto[1] |
auto[0] |
1754718 |
1 |
|
|
T24 |
2 |
|
T1 |
31 |
|
T12 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1234123 |
1 |
|
|
T24 |
1 |
|
T1 |
309 |
|
T12 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |