Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146844 |
1 |
|
|
T23 |
254 |
|
T24 |
76 |
|
T25 |
110 |
| auto[1] |
5974124 |
1 |
|
|
T24 |
17 |
|
T1 |
530 |
|
T12 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655449 |
1 |
|
|
T23 |
254 |
|
T24 |
84 |
|
T25 |
110 |
| auto[1] |
2465519 |
1 |
|
|
T24 |
9 |
|
T1 |
426 |
|
T12 |
57 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8152769 |
1 |
|
|
T23 |
254 |
|
T24 |
83 |
|
T25 |
110 |
| auto[1] |
5968199 |
1 |
|
|
T24 |
10 |
|
T1 |
486 |
|
T12 |
119 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1757498 |
1 |
|
|
T1 |
29 |
|
T12 |
14 |
|
T14 |
207 |
| auto[1] |
auto[0] |
auto[1] |
1236988 |
1 |
|
|
T24 |
4 |
|
T1 |
245 |
|
T12 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1745182 |
1 |
|
|
T24 |
1 |
|
T1 |
31 |
|
T12 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1228531 |
1 |
|
|
T24 |
5 |
|
T1 |
181 |
|
T12 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |