Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8159981 |
1 |
|
|
T23 |
254 |
|
T24 |
46 |
|
T25 |
110 |
| auto[1] |
5960987 |
1 |
|
|
T24 |
47 |
|
T1 |
603 |
|
T12 |
198 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11666668 |
1 |
|
|
T23 |
254 |
|
T24 |
82 |
|
T25 |
110 |
| auto[1] |
2454300 |
1 |
|
|
T24 |
11 |
|
T1 |
284 |
|
T12 |
107 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8168690 |
1 |
|
|
T23 |
254 |
|
T24 |
40 |
|
T25 |
110 |
| auto[1] |
5952278 |
1 |
|
|
T24 |
53 |
|
T1 |
330 |
|
T12 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1761995 |
1 |
|
|
T24 |
12 |
|
T1 |
24 |
|
T12 |
30 |
| auto[1] |
auto[0] |
auto[1] |
1237421 |
1 |
|
|
T24 |
2 |
|
T1 |
149 |
|
T12 |
46 |
| auto[1] |
auto[1] |
auto[0] |
1735983 |
1 |
|
|
T24 |
30 |
|
T1 |
22 |
|
T12 |
46 |
| auto[1] |
auto[1] |
auto[1] |
1216879 |
1 |
|
|
T24 |
9 |
|
T1 |
135 |
|
T12 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |