Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8157262 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5963706 |
1 |
|
|
T24 |
33 |
|
T1 |
529 |
|
T12 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660413 |
1 |
|
|
T23 |
254 |
|
T24 |
83 |
|
T25 |
110 |
| auto[1] |
2460555 |
1 |
|
|
T24 |
10 |
|
T1 |
478 |
|
T12 |
116 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8167305 |
1 |
|
|
T23 |
254 |
|
T24 |
51 |
|
T25 |
110 |
| auto[1] |
5953663 |
1 |
|
|
T24 |
42 |
|
T1 |
614 |
|
T12 |
241 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1748055 |
1 |
|
|
T24 |
15 |
|
T1 |
74 |
|
T12 |
61 |
| auto[1] |
auto[0] |
auto[1] |
1229743 |
1 |
|
|
T24 |
6 |
|
T1 |
240 |
|
T12 |
35 |
| auto[1] |
auto[1] |
auto[0] |
1745053 |
1 |
|
|
T24 |
17 |
|
T1 |
62 |
|
T12 |
64 |
| auto[1] |
auto[1] |
auto[1] |
1230812 |
1 |
|
|
T24 |
4 |
|
T1 |
238 |
|
T12 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |