Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8146736 |
1 |
|
|
T23 |
254 |
|
T24 |
59 |
|
T25 |
110 |
| auto[1] |
5974232 |
1 |
|
|
T24 |
34 |
|
T1 |
640 |
|
T12 |
166 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662770 |
1 |
|
|
T23 |
254 |
|
T24 |
84 |
|
T25 |
110 |
| auto[1] |
2458198 |
1 |
|
|
T24 |
9 |
|
T1 |
423 |
|
T12 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166423 |
1 |
|
|
T23 |
254 |
|
T24 |
81 |
|
T25 |
110 |
| auto[1] |
5954545 |
1 |
|
|
T24 |
12 |
|
T1 |
571 |
|
T12 |
138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1749744 |
1 |
|
|
T1 |
73 |
|
T12 |
44 |
|
T14 |
272 |
| auto[1] |
auto[0] |
auto[1] |
1228192 |
1 |
|
|
T24 |
6 |
|
T1 |
196 |
|
T12 |
26 |
| auto[1] |
auto[1] |
auto[0] |
1746603 |
1 |
|
|
T24 |
3 |
|
T1 |
75 |
|
T12 |
29 |
| auto[1] |
auto[1] |
auto[1] |
1230006 |
1 |
|
|
T24 |
3 |
|
T1 |
227 |
|
T12 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |