Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8144946 |
1 |
|
|
T23 |
254 |
|
T24 |
49 |
|
T25 |
110 |
| auto[1] |
5976022 |
1 |
|
|
T24 |
44 |
|
T1 |
521 |
|
T12 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11640849 |
1 |
|
|
T23 |
254 |
|
T24 |
71 |
|
T25 |
110 |
| auto[1] |
2480119 |
1 |
|
|
T24 |
22 |
|
T1 |
390 |
|
T12 |
113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8097952 |
1 |
|
|
T23 |
254 |
|
T24 |
57 |
|
T25 |
110 |
| auto[1] |
6023016 |
1 |
|
|
T24 |
36 |
|
T1 |
511 |
|
T12 |
165 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1775143 |
1 |
|
|
T24 |
3 |
|
T1 |
59 |
|
T12 |
29 |
| auto[1] |
auto[0] |
auto[1] |
1244432 |
1 |
|
|
T24 |
11 |
|
T1 |
186 |
|
T12 |
63 |
| auto[1] |
auto[1] |
auto[0] |
1767754 |
1 |
|
|
T24 |
11 |
|
T1 |
62 |
|
T12 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1235687 |
1 |
|
|
T24 |
11 |
|
T1 |
204 |
|
T12 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |