Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136833 |
1 |
|
|
T23 |
254 |
|
T24 |
39 |
|
T25 |
110 |
| auto[1] |
5984135 |
1 |
|
|
T24 |
54 |
|
T1 |
629 |
|
T12 |
185 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11641673 |
1 |
|
|
T23 |
254 |
|
T24 |
73 |
|
T25 |
110 |
| auto[1] |
2479295 |
1 |
|
|
T24 |
20 |
|
T1 |
265 |
|
T12 |
100 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8122563 |
1 |
|
|
T23 |
254 |
|
T24 |
69 |
|
T25 |
110 |
| auto[1] |
5998405 |
1 |
|
|
T24 |
24 |
|
T1 |
426 |
|
T12 |
142 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1762437 |
1 |
|
|
T24 |
2 |
|
T1 |
60 |
|
T12 |
21 |
| auto[1] |
auto[0] |
auto[1] |
1241565 |
1 |
|
|
T24 |
7 |
|
T1 |
103 |
|
T12 |
44 |
| auto[1] |
auto[1] |
auto[0] |
1756673 |
1 |
|
|
T24 |
2 |
|
T1 |
101 |
|
T12 |
21 |
| auto[1] |
auto[1] |
auto[1] |
1237730 |
1 |
|
|
T24 |
13 |
|
T1 |
162 |
|
T12 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |