Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8154151 |
1 |
|
|
T23 |
254 |
|
T24 |
71 |
|
T25 |
110 |
| auto[1] |
5966817 |
1 |
|
|
T24 |
22 |
|
T1 |
601 |
|
T12 |
251 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659508 |
1 |
|
|
T23 |
254 |
|
T24 |
75 |
|
T25 |
110 |
| auto[1] |
2461460 |
1 |
|
|
T24 |
18 |
|
T1 |
343 |
|
T12 |
69 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8151795 |
1 |
|
|
T23 |
254 |
|
T24 |
54 |
|
T25 |
110 |
| auto[1] |
5969173 |
1 |
|
|
T24 |
39 |
|
T1 |
436 |
|
T12 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1751612 |
1 |
|
|
T24 |
21 |
|
T1 |
51 |
|
T12 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1231810 |
1 |
|
|
T24 |
4 |
|
T1 |
202 |
|
T12 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1756101 |
1 |
|
|
T1 |
42 |
|
T12 |
44 |
|
T14 |
124 |
| auto[1] |
auto[1] |
auto[1] |
1229650 |
1 |
|
|
T24 |
14 |
|
T1 |
141 |
|
T12 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |