Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8142206 |
1 |
|
|
T23 |
254 |
|
T24 |
74 |
|
T25 |
110 |
| auto[1] |
5978762 |
1 |
|
|
T24 |
19 |
|
T1 |
575 |
|
T12 |
180 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664050 |
1 |
|
|
T23 |
254 |
|
T24 |
89 |
|
T25 |
110 |
| auto[1] |
2456918 |
1 |
|
|
T24 |
4 |
|
T1 |
509 |
|
T12 |
84 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8195459 |
1 |
|
|
T23 |
254 |
|
T24 |
79 |
|
T25 |
110 |
| auto[1] |
5925509 |
1 |
|
|
T24 |
14 |
|
T1 |
621 |
|
T12 |
169 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1729381 |
1 |
|
|
T24 |
10 |
|
T1 |
69 |
|
T12 |
45 |
| auto[1] |
auto[0] |
auto[1] |
1228835 |
1 |
|
|
T1 |
240 |
|
T12 |
28 |
|
T14 |
190 |
| auto[1] |
auto[1] |
auto[0] |
1739210 |
1 |
|
|
T1 |
43 |
|
T12 |
40 |
|
T14 |
114 |
| auto[1] |
auto[1] |
auto[1] |
1228083 |
1 |
|
|
T24 |
4 |
|
T1 |
269 |
|
T12 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |