Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138871 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5982097 |
1 |
|
|
T24 |
33 |
|
T1 |
742 |
|
T12 |
180 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664159 |
1 |
|
|
T23 |
254 |
|
T24 |
77 |
|
T25 |
110 |
| auto[1] |
2456809 |
1 |
|
|
T24 |
16 |
|
T1 |
463 |
|
T12 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8171904 |
1 |
|
|
T23 |
254 |
|
T24 |
52 |
|
T25 |
110 |
| auto[1] |
5949064 |
1 |
|
|
T24 |
41 |
|
T1 |
582 |
|
T12 |
171 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1755363 |
1 |
|
|
T24 |
11 |
|
T1 |
52 |
|
T12 |
49 |
| auto[1] |
auto[0] |
auto[1] |
1237540 |
1 |
|
|
T24 |
4 |
|
T1 |
157 |
|
T12 |
24 |
| auto[1] |
auto[1] |
auto[0] |
1736892 |
1 |
|
|
T24 |
14 |
|
T1 |
67 |
|
T12 |
57 |
| auto[1] |
auto[1] |
auto[1] |
1219269 |
1 |
|
|
T24 |
12 |
|
T1 |
306 |
|
T12 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |