Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8144609 |
1 |
|
|
T23 |
254 |
|
T24 |
62 |
|
T25 |
110 |
| auto[1] |
5976359 |
1 |
|
|
T24 |
31 |
|
T1 |
607 |
|
T12 |
190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13362186 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
758782 |
1 |
|
|
T1 |
37 |
|
T12 |
13 |
|
T14 |
137 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181029 |
1 |
|
|
T23 |
254 |
|
T24 |
81 |
|
T25 |
110 |
| auto[1] |
5939939 |
1 |
|
|
T24 |
12 |
|
T1 |
650 |
|
T12 |
161 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2590153 |
1 |
|
|
T24 |
3 |
|
T1 |
265 |
|
T12 |
43 |
| auto[1] |
auto[0] |
auto[1] |
380559 |
1 |
|
|
T1 |
17 |
|
T12 |
2 |
|
T14 |
92 |
| auto[1] |
auto[1] |
auto[0] |
2591004 |
1 |
|
|
T24 |
9 |
|
T1 |
348 |
|
T12 |
105 |
| auto[1] |
auto[1] |
auto[1] |
378223 |
1 |
|
|
T1 |
20 |
|
T12 |
11 |
|
T14 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |