Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8116166 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
6004802 |
1 |
|
|
T24 |
33 |
|
T1 |
466 |
|
T12 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11648517 |
1 |
|
|
T23 |
254 |
|
T24 |
78 |
|
T25 |
110 |
| auto[1] |
2472451 |
1 |
|
|
T24 |
15 |
|
T1 |
457 |
|
T12 |
59 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8121575 |
1 |
|
|
T23 |
254 |
|
T24 |
55 |
|
T25 |
110 |
| auto[1] |
5999393 |
1 |
|
|
T24 |
38 |
|
T1 |
629 |
|
T12 |
119 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1754833 |
1 |
|
|
T24 |
15 |
|
T1 |
102 |
|
T12 |
18 |
| auto[1] |
auto[0] |
auto[1] |
1234857 |
1 |
|
|
T24 |
3 |
|
T1 |
262 |
|
T12 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1772109 |
1 |
|
|
T24 |
8 |
|
T1 |
70 |
|
T12 |
42 |
| auto[1] |
auto[1] |
auto[1] |
1237594 |
1 |
|
|
T24 |
12 |
|
T1 |
195 |
|
T12 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |