Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8091776 |
1 |
|
|
T23 |
254 |
|
T24 |
66 |
|
T25 |
110 |
| auto[1] |
6029192 |
1 |
|
|
T24 |
27 |
|
T1 |
697 |
|
T12 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659484 |
1 |
|
|
T23 |
254 |
|
T24 |
79 |
|
T25 |
110 |
| auto[1] |
2461484 |
1 |
|
|
T24 |
14 |
|
T1 |
542 |
|
T12 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8163565 |
1 |
|
|
T23 |
254 |
|
T24 |
50 |
|
T25 |
110 |
| auto[1] |
5957403 |
1 |
|
|
T24 |
43 |
|
T1 |
666 |
|
T12 |
118 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1740463 |
1 |
|
|
T24 |
9 |
|
T1 |
42 |
|
T12 |
32 |
| auto[1] |
auto[0] |
auto[1] |
1223784 |
1 |
|
|
T24 |
13 |
|
T1 |
227 |
|
T12 |
31 |
| auto[1] |
auto[1] |
auto[0] |
1755456 |
1 |
|
|
T24 |
20 |
|
T1 |
82 |
|
T12 |
41 |
| auto[1] |
auto[1] |
auto[1] |
1237700 |
1 |
|
|
T24 |
1 |
|
T1 |
315 |
|
T12 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |