Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8130879 |
1 |
|
|
T23 |
254 |
|
T24 |
62 |
|
T25 |
110 |
| auto[1] |
5990089 |
1 |
|
|
T24 |
31 |
|
T1 |
557 |
|
T12 |
165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11646715 |
1 |
|
|
T23 |
254 |
|
T24 |
85 |
|
T25 |
110 |
| auto[1] |
2474253 |
1 |
|
|
T24 |
8 |
|
T1 |
527 |
|
T12 |
111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8140470 |
1 |
|
|
T23 |
254 |
|
T24 |
73 |
|
T25 |
110 |
| auto[1] |
5980498 |
1 |
|
|
T24 |
20 |
|
T1 |
658 |
|
T12 |
199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1750647 |
1 |
|
|
T24 |
12 |
|
T1 |
66 |
|
T12 |
36 |
| auto[1] |
auto[0] |
auto[1] |
1234525 |
1 |
|
|
T24 |
8 |
|
T1 |
266 |
|
T12 |
56 |
| auto[1] |
auto[1] |
auto[0] |
1755598 |
1 |
|
|
T1 |
65 |
|
T12 |
52 |
|
T14 |
194 |
| auto[1] |
auto[1] |
auto[1] |
1239728 |
1 |
|
|
T1 |
261 |
|
T12 |
55 |
|
T14 |
163 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |