Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8116790 |
1 |
|
|
T23 |
254 |
|
T24 |
59 |
|
T25 |
110 |
| auto[1] |
6004178 |
1 |
|
|
T24 |
34 |
|
T1 |
622 |
|
T12 |
84 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13364227 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
756741 |
1 |
|
|
T24 |
1 |
|
T1 |
20 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8177077 |
1 |
|
|
T23 |
254 |
|
T24 |
63 |
|
T25 |
110 |
| auto[1] |
5943891 |
1 |
|
|
T24 |
30 |
|
T1 |
467 |
|
T12 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2586019 |
1 |
|
|
T24 |
23 |
|
T1 |
270 |
|
T12 |
82 |
| auto[1] |
auto[0] |
auto[1] |
376367 |
1 |
|
|
T1 |
11 |
|
T12 |
8 |
|
T14 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2601131 |
1 |
|
|
T24 |
6 |
|
T1 |
177 |
|
T12 |
24 |
| auto[1] |
auto[1] |
auto[1] |
380374 |
1 |
|
|
T24 |
1 |
|
T1 |
9 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |