Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8151408 |
1 |
|
|
T23 |
254 |
|
T24 |
69 |
|
T25 |
110 |
| auto[1] |
5969560 |
1 |
|
|
T24 |
24 |
|
T1 |
442 |
|
T12 |
163 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13358905 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
762063 |
1 |
|
|
T1 |
26 |
|
T12 |
8 |
|
T14 |
101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8162509 |
1 |
|
|
T23 |
254 |
|
T24 |
63 |
|
T25 |
110 |
| auto[1] |
5958459 |
1 |
|
|
T24 |
30 |
|
T1 |
600 |
|
T12 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2610951 |
1 |
|
|
T24 |
21 |
|
T1 |
382 |
|
T12 |
31 |
| auto[1] |
auto[0] |
auto[1] |
383189 |
1 |
|
|
T1 |
15 |
|
T12 |
2 |
|
T14 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2585445 |
1 |
|
|
T24 |
9 |
|
T1 |
192 |
|
T12 |
57 |
| auto[1] |
auto[1] |
auto[1] |
378874 |
1 |
|
|
T1 |
11 |
|
T12 |
6 |
|
T14 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |