Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8142429 |
1 |
|
|
T23 |
254 |
|
T24 |
77 |
|
T25 |
110 |
| auto[1] |
5978539 |
1 |
|
|
T24 |
16 |
|
T1 |
421 |
|
T12 |
186 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13352181 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
768787 |
1 |
|
|
T24 |
1 |
|
T1 |
21 |
|
T12 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8109587 |
1 |
|
|
T23 |
254 |
|
T24 |
57 |
|
T25 |
110 |
| auto[1] |
6011381 |
1 |
|
|
T24 |
36 |
|
T1 |
496 |
|
T12 |
172 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2616398 |
1 |
|
|
T24 |
27 |
|
T1 |
316 |
|
T12 |
62 |
| auto[1] |
auto[0] |
auto[1] |
382926 |
1 |
|
|
T24 |
1 |
|
T1 |
14 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2626196 |
1 |
|
|
T24 |
8 |
|
T1 |
159 |
|
T12 |
96 |
| auto[1] |
auto[1] |
auto[1] |
385861 |
1 |
|
|
T1 |
7 |
|
T12 |
10 |
|
T14 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |