Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8153418 |
1 |
|
|
T23 |
254 |
|
T24 |
66 |
|
T25 |
110 |
| auto[1] |
5967550 |
1 |
|
|
T24 |
27 |
|
T1 |
592 |
|
T12 |
166 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13363379 |
1 |
|
|
T23 |
254 |
|
T24 |
91 |
|
T25 |
110 |
| auto[1] |
757589 |
1 |
|
|
T24 |
2 |
|
T1 |
20 |
|
T12 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178276 |
1 |
|
|
T23 |
254 |
|
T24 |
50 |
|
T25 |
110 |
| auto[1] |
5942692 |
1 |
|
|
T24 |
43 |
|
T1 |
573 |
|
T12 |
139 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2604243 |
1 |
|
|
T24 |
35 |
|
T1 |
244 |
|
T12 |
43 |
| auto[1] |
auto[0] |
auto[1] |
380209 |
1 |
|
|
T1 |
8 |
|
T12 |
5 |
|
T14 |
71 |
| auto[1] |
auto[1] |
auto[0] |
2580860 |
1 |
|
|
T24 |
6 |
|
T1 |
309 |
|
T12 |
85 |
| auto[1] |
auto[1] |
auto[1] |
377380 |
1 |
|
|
T24 |
2 |
|
T1 |
12 |
|
T12 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |