Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8150404 |
1 |
|
|
T23 |
254 |
|
T24 |
47 |
|
T25 |
110 |
| auto[1] |
5970564 |
1 |
|
|
T24 |
46 |
|
T1 |
477 |
|
T12 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13356360 |
1 |
|
|
T23 |
254 |
|
T24 |
92 |
|
T25 |
110 |
| auto[1] |
764608 |
1 |
|
|
T24 |
1 |
|
T1 |
20 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8144346 |
1 |
|
|
T23 |
254 |
|
T24 |
60 |
|
T25 |
110 |
| auto[1] |
5976622 |
1 |
|
|
T24 |
33 |
|
T1 |
580 |
|
T12 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614030 |
1 |
|
|
T24 |
24 |
|
T1 |
325 |
|
T12 |
103 |
| auto[1] |
auto[0] |
auto[1] |
384294 |
1 |
|
|
T1 |
7 |
|
T12 |
6 |
|
T14 |
41 |
| auto[1] |
auto[1] |
auto[0] |
2597984 |
1 |
|
|
T24 |
8 |
|
T1 |
235 |
|
T12 |
71 |
| auto[1] |
auto[1] |
auto[1] |
380314 |
1 |
|
|
T24 |
1 |
|
T1 |
13 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |