Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8176907 |
1 |
|
|
T23 |
254 |
|
T24 |
59 |
|
T25 |
110 |
| auto[1] |
5944061 |
1 |
|
|
T24 |
34 |
|
T1 |
576 |
|
T12 |
99 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13360490 |
1 |
|
|
T23 |
254 |
|
T24 |
93 |
|
T25 |
110 |
| auto[1] |
760478 |
1 |
|
|
T1 |
28 |
|
T12 |
4 |
|
T14 |
115 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8160630 |
1 |
|
|
T23 |
254 |
|
T24 |
55 |
|
T25 |
110 |
| auto[1] |
5960338 |
1 |
|
|
T24 |
38 |
|
T1 |
635 |
|
T12 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614095 |
1 |
|
|
T24 |
22 |
|
T1 |
298 |
|
T12 |
58 |
| auto[1] |
auto[0] |
auto[1] |
382526 |
1 |
|
|
T1 |
14 |
|
T12 |
4 |
|
T14 |
49 |
| auto[1] |
auto[1] |
auto[0] |
2585765 |
1 |
|
|
T24 |
16 |
|
T1 |
309 |
|
T12 |
34 |
| auto[1] |
auto[1] |
auto[1] |
377952 |
1 |
|
|
T1 |
14 |
|
T14 |
66 |
|
T17 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |