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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
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T763 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3881622800 Jun 09 12:42:32 PM PDT 24 Jun 09 12:42:33 PM PDT 24 11603822 ps
T764 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.669718357 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:56 PM PDT 24 103593057 ps
T765 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2593929473 Jun 09 12:42:51 PM PDT 24 Jun 09 12:42:52 PM PDT 24 35468167 ps
T766 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2155652194 Jun 09 12:42:53 PM PDT 24 Jun 09 12:42:54 PM PDT 24 18172075 ps
T43 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1225849271 Jun 09 12:42:16 PM PDT 24 Jun 09 12:42:17 PM PDT 24 209875995 ps
T78 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4003289537 Jun 09 12:42:28 PM PDT 24 Jun 09 12:42:29 PM PDT 24 25830301 ps
T767 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1277351688 Jun 09 12:42:39 PM PDT 24 Jun 09 12:42:40 PM PDT 24 20814451 ps
T768 /workspace/coverage/cover_reg_top/47.gpio_intr_test.431765157 Jun 09 12:42:59 PM PDT 24 Jun 09 12:43:00 PM PDT 24 14238928 ps
T769 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1513789024 Jun 09 12:42:55 PM PDT 24 Jun 09 12:42:56 PM PDT 24 46167318 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2591009555 Jun 09 12:42:23 PM PDT 24 Jun 09 12:42:27 PM PDT 24 1675737469 ps
T771 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2304812944 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:56 PM PDT 24 123831095 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1144035909 Jun 09 12:42:21 PM PDT 24 Jun 09 12:42:22 PM PDT 24 34233283 ps
T79 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1087418033 Jun 09 12:42:29 PM PDT 24 Jun 09 12:42:30 PM PDT 24 53446350 ps
T773 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1902208318 Jun 09 12:42:32 PM PDT 24 Jun 09 12:42:33 PM PDT 24 28372021 ps
T774 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3389484715 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:56 PM PDT 24 772192124 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1482770159 Jun 09 12:42:16 PM PDT 24 Jun 09 12:42:17 PM PDT 24 22058042 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3515603586 Jun 09 12:42:47 PM PDT 24 Jun 09 12:42:48 PM PDT 24 67611339 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4228679179 Jun 09 12:42:21 PM PDT 24 Jun 09 12:42:22 PM PDT 24 22559974 ps
T778 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1692888275 Jun 09 12:42:20 PM PDT 24 Jun 09 12:42:21 PM PDT 24 18238284 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3605171759 Jun 09 12:42:33 PM PDT 24 Jun 09 12:42:36 PM PDT 24 110265042 ps
T80 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.612405090 Jun 09 12:42:48 PM PDT 24 Jun 09 12:42:49 PM PDT 24 45016717 ps
T780 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1455175464 Jun 09 12:42:52 PM PDT 24 Jun 09 12:42:53 PM PDT 24 87108800 ps
T81 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1231901507 Jun 09 12:42:42 PM PDT 24 Jun 09 12:42:43 PM PDT 24 14148664 ps
T781 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2166782138 Jun 09 12:42:52 PM PDT 24 Jun 09 12:42:53 PM PDT 24 11743239 ps
T782 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3443681500 Jun 09 12:42:53 PM PDT 24 Jun 09 12:42:54 PM PDT 24 40942405 ps
T783 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3387845290 Jun 09 12:42:44 PM PDT 24 Jun 09 12:42:45 PM PDT 24 14335208 ps
T784 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3363425701 Jun 09 12:42:58 PM PDT 24 Jun 09 12:42:59 PM PDT 24 14059761 ps
T785 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3295295896 Jun 09 12:42:48 PM PDT 24 Jun 09 12:42:49 PM PDT 24 116125832 ps
T82 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1961944227 Jun 09 12:42:49 PM PDT 24 Jun 09 12:42:50 PM PDT 24 18640852 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.569463240 Jun 09 12:42:47 PM PDT 24 Jun 09 12:42:48 PM PDT 24 21191054 ps
T83 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.105435938 Jun 09 12:42:33 PM PDT 24 Jun 09 12:42:34 PM PDT 24 16069429 ps
T787 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1783934935 Jun 09 12:42:33 PM PDT 24 Jun 09 12:42:34 PM PDT 24 172320553 ps
T788 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3183643954 Jun 09 12:42:43 PM PDT 24 Jun 09 12:42:44 PM PDT 24 40507701 ps
T789 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1835675650 Jun 09 12:42:42 PM PDT 24 Jun 09 12:42:45 PM PDT 24 560572178 ps
T790 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1197401503 Jun 09 12:42:51 PM PDT 24 Jun 09 12:42:55 PM PDT 24 54742835 ps
T791 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3409589820 Jun 09 12:42:46 PM PDT 24 Jun 09 12:42:47 PM PDT 24 46612779 ps
T792 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2922639871 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:55 PM PDT 24 17326303 ps
T793 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1217011581 Jun 09 12:42:44 PM PDT 24 Jun 09 12:42:45 PM PDT 24 44763565 ps
T794 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2580783564 Jun 09 12:42:44 PM PDT 24 Jun 09 12:42:46 PM PDT 24 28000845 ps
T795 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1259764556 Jun 09 12:42:17 PM PDT 24 Jun 09 12:42:19 PM PDT 24 65067598 ps
T44 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1801497578 Jun 09 12:42:38 PM PDT 24 Jun 09 12:42:40 PM PDT 24 377151306 ps
T796 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2025682415 Jun 09 12:42:28 PM PDT 24 Jun 09 12:42:30 PM PDT 24 21504535 ps
T797 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3158661236 Jun 09 12:42:15 PM PDT 24 Jun 09 12:42:16 PM PDT 24 73236942 ps
T798 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.385034006 Jun 09 12:42:23 PM PDT 24 Jun 09 12:42:24 PM PDT 24 66692373 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1728538564 Jun 09 12:42:43 PM PDT 24 Jun 09 12:42:46 PM PDT 24 126478317 ps
T800 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3980241200 Jun 09 12:42:29 PM PDT 24 Jun 09 12:42:31 PM PDT 24 61219843 ps
T801 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1468649854 Jun 09 12:42:53 PM PDT 24 Jun 09 12:42:54 PM PDT 24 340067466 ps
T802 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3460291292 Jun 09 12:42:36 PM PDT 24 Jun 09 12:42:40 PM PDT 24 610407998 ps
T803 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3884889578 Jun 09 12:42:49 PM PDT 24 Jun 09 12:42:50 PM PDT 24 13002397 ps
T804 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1166537086 Jun 09 12:42:37 PM PDT 24 Jun 09 12:42:38 PM PDT 24 47569661 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2260618399 Jun 09 12:42:24 PM PDT 24 Jun 09 12:42:27 PM PDT 24 229179752 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2015098139 Jun 09 12:42:16 PM PDT 24 Jun 09 12:42:17 PM PDT 24 31764789 ps
T807 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2329874317 Jun 09 12:42:48 PM PDT 24 Jun 09 12:42:49 PM PDT 24 293513183 ps
T808 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3077748993 Jun 09 12:43:00 PM PDT 24 Jun 09 12:43:01 PM PDT 24 12765462 ps
T809 /workspace/coverage/cover_reg_top/2.gpio_intr_test.4248804050 Jun 09 12:42:24 PM PDT 24 Jun 09 12:42:25 PM PDT 24 30411000 ps
T810 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1998755571 Jun 09 12:42:41 PM PDT 24 Jun 09 12:42:42 PM PDT 24 338275373 ps
T811 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1637856848 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:56 PM PDT 24 18288560 ps
T812 /workspace/coverage/cover_reg_top/42.gpio_intr_test.975083645 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:55 PM PDT 24 133972830 ps
T813 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2501389618 Jun 09 12:42:33 PM PDT 24 Jun 09 12:42:35 PM PDT 24 108710134 ps
T814 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.738409639 Jun 09 12:42:50 PM PDT 24 Jun 09 12:42:53 PM PDT 24 130058508 ps
T84 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1212955547 Jun 09 12:42:29 PM PDT 24 Jun 09 12:42:31 PM PDT 24 33218386 ps
T815 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1806543666 Jun 09 12:42:39 PM PDT 24 Jun 09 12:42:41 PM PDT 24 66057981 ps
T816 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3362561422 Jun 09 12:42:22 PM PDT 24 Jun 09 12:42:23 PM PDT 24 59768805 ps
T103 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1756248572 Jun 09 12:42:48 PM PDT 24 Jun 09 12:42:49 PM PDT 24 143329095 ps
T817 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3898308749 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:55 PM PDT 24 31168640 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3984517655 Jun 09 12:42:41 PM PDT 24 Jun 09 12:42:42 PM PDT 24 477102170 ps
T45 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.851368945 Jun 09 12:42:30 PM PDT 24 Jun 09 12:42:32 PM PDT 24 87825906 ps
T819 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3826991745 Jun 09 12:42:51 PM PDT 24 Jun 09 12:42:54 PM PDT 24 47401877 ps
T820 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.968984437 Jun 09 12:42:19 PM PDT 24 Jun 09 12:42:20 PM PDT 24 44461036 ps
T821 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2006665836 Jun 09 12:42:29 PM PDT 24 Jun 09 12:42:31 PM PDT 24 961168902 ps
T822 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2561851753 Jun 09 12:42:58 PM PDT 24 Jun 09 12:42:59 PM PDT 24 41624311 ps
T823 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1864669658 Jun 09 12:42:57 PM PDT 24 Jun 09 12:42:58 PM PDT 24 33027803 ps
T824 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2329312189 Jun 09 12:42:56 PM PDT 24 Jun 09 12:42:57 PM PDT 24 14519741 ps
T85 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2985192834 Jun 09 12:42:24 PM PDT 24 Jun 09 12:42:25 PM PDT 24 24097774 ps
T825 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1957171937 Jun 09 12:42:33 PM PDT 24 Jun 09 12:42:35 PM PDT 24 835473461 ps
T826 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2561408777 Jun 09 12:42:38 PM PDT 24 Jun 09 12:42:38 PM PDT 24 17947626 ps
T827 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3415318556 Jun 09 12:42:38 PM PDT 24 Jun 09 12:42:39 PM PDT 24 204592420 ps
T828 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1058595830 Jun 09 12:42:31 PM PDT 24 Jun 09 12:42:32 PM PDT 24 35241499 ps
T829 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3712921271 Jun 09 12:42:46 PM PDT 24 Jun 09 12:42:46 PM PDT 24 14373997 ps
T830 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.257326146 Jun 09 12:42:34 PM PDT 24 Jun 09 12:42:35 PM PDT 24 59850917 ps
T831 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.554297683 Jun 09 12:42:48 PM PDT 24 Jun 09 12:42:49 PM PDT 24 133444878 ps
T832 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3202923704 Jun 09 12:42:41 PM PDT 24 Jun 09 12:42:42 PM PDT 24 31569554 ps
T833 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3626079586 Jun 09 12:42:49 PM PDT 24 Jun 09 12:42:52 PM PDT 24 309711886 ps
T834 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1339150873 Jun 09 12:42:54 PM PDT 24 Jun 09 12:42:56 PM PDT 24 40310936 ps
T835 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1692965376 Jun 09 12:42:42 PM PDT 24 Jun 09 12:42:43 PM PDT 24 203905732 ps
T836 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3081444476 Jun 09 12:42:39 PM PDT 24 Jun 09 12:42:41 PM PDT 24 388587459 ps
T837 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2072117648 Jun 09 12:42:50 PM PDT 24 Jun 09 12:42:52 PM PDT 24 129023717 ps
T838 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.809660010 Jun 09 12:42:49 PM PDT 24 Jun 09 12:42:51 PM PDT 24 28407415 ps
T839 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2349873428 Jun 09 12:42:34 PM PDT 24 Jun 09 12:42:35 PM PDT 24 30452112 ps
T840 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3449582788 Jun 09 12:42:14 PM PDT 24 Jun 09 12:42:15 PM PDT 24 82092781 ps
T841 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.705236935 Jun 09 12:42:50 PM PDT 24 Jun 09 12:42:52 PM PDT 24 954079948 ps
T842 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2549771587 Jun 09 12:42:23 PM PDT 24 Jun 09 12:42:27 PM PDT 24 1348327360 ps
T843 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.975263313 Jun 09 12:33:20 PM PDT 24 Jun 09 12:33:22 PM PDT 24 295663289 ps
T844 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907945489 Jun 09 12:33:09 PM PDT 24 Jun 09 12:33:11 PM PDT 24 44604291 ps
T845 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3586117502 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 47765332 ps
T846 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2648129803 Jun 09 12:33:33 PM PDT 24 Jun 09 12:33:34 PM PDT 24 48868951 ps
T847 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4158899535 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 175715771 ps
T848 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1000433456 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 280917964 ps
T849 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1289000658 Jun 09 12:33:09 PM PDT 24 Jun 09 12:33:11 PM PDT 24 43852827 ps
T850 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1334211725 Jun 09 12:33:11 PM PDT 24 Jun 09 12:33:12 PM PDT 24 53394361 ps
T851 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3643313185 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:18 PM PDT 24 105282839 ps
T852 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1621514798 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:16 PM PDT 24 316935867 ps
T853 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.395971463 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:16 PM PDT 24 50460009 ps
T854 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1677371632 Jun 09 12:33:05 PM PDT 24 Jun 09 12:33:06 PM PDT 24 178535848 ps
T855 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1947863161 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 325270972 ps
T856 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.312807564 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:24 PM PDT 24 447509905 ps
T857 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.744394270 Jun 09 12:33:19 PM PDT 24 Jun 09 12:33:20 PM PDT 24 64656563 ps
T858 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3289323991 Jun 09 12:33:09 PM PDT 24 Jun 09 12:33:10 PM PDT 24 87404715 ps
T859 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3234883167 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 56685810 ps
T860 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093764782 Jun 09 12:33:15 PM PDT 24 Jun 09 12:33:17 PM PDT 24 273576840 ps
T861 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3048344161 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:18 PM PDT 24 131700892 ps
T862 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4210100402 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:16 PM PDT 24 86688928 ps
T863 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3314768757 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 48361521 ps
T864 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3507392388 Jun 09 12:33:08 PM PDT 24 Jun 09 12:33:10 PM PDT 24 129233260 ps
T865 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3853841724 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 71314885 ps
T866 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2403839743 Jun 09 12:33:10 PM PDT 24 Jun 09 12:33:11 PM PDT 24 78548717 ps
T867 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.105505841 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 179830772 ps
T868 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482188308 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 228581111 ps
T869 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618679706 Jun 09 12:33:30 PM PDT 24 Jun 09 12:33:32 PM PDT 24 94847579 ps
T870 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1847742034 Jun 09 12:33:12 PM PDT 24 Jun 09 12:33:13 PM PDT 24 180925037 ps
T871 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2282428730 Jun 09 12:33:10 PM PDT 24 Jun 09 12:33:11 PM PDT 24 243839364 ps
T872 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3140031282 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 103336679 ps
T873 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1742362965 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 533974543 ps
T874 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4107692025 Jun 09 12:33:15 PM PDT 24 Jun 09 12:33:17 PM PDT 24 102474401 ps
T875 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2449558067 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:16 PM PDT 24 102147368 ps
T876 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1405753404 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:16 PM PDT 24 145143374 ps
T877 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2598763521 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 298203436 ps
T878 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3770111764 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:18 PM PDT 24 53644575 ps
T879 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4110543121 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 296245295 ps
T880 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2241569555 Jun 09 12:33:09 PM PDT 24 Jun 09 12:33:11 PM PDT 24 51672179 ps
T881 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3574442713 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 61796596 ps
T882 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1781035127 Jun 09 12:33:11 PM PDT 24 Jun 09 12:33:12 PM PDT 24 81001126 ps
T883 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2960278296 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 50083524 ps
T884 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.647131951 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 349066938 ps
T885 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.437081789 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 147526807 ps
T886 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2915566707 Jun 09 12:33:08 PM PDT 24 Jun 09 12:33:10 PM PDT 24 69449807 ps
T887 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1851008729 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 344719267 ps
T888 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3355043563 Jun 09 12:33:09 PM PDT 24 Jun 09 12:33:10 PM PDT 24 117336387 ps
T889 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3106533173 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:19 PM PDT 24 157790841 ps
T890 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1690420996 Jun 09 12:33:36 PM PDT 24 Jun 09 12:33:38 PM PDT 24 70908220 ps
T891 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3692289782 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 304127343 ps
T892 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2347329422 Jun 09 12:33:30 PM PDT 24 Jun 09 12:33:31 PM PDT 24 174836540 ps
T893 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3413787958 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:20 PM PDT 24 594000996 ps
T894 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1357833101 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:15 PM PDT 24 156832713 ps
T895 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3871959655 Jun 09 12:33:25 PM PDT 24 Jun 09 12:33:26 PM PDT 24 54992288 ps
T896 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.745696396 Jun 09 12:33:10 PM PDT 24 Jun 09 12:33:11 PM PDT 24 63830411 ps
T897 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3337993786 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 61401847 ps
T898 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2080426389 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 120121454 ps
T899 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3213611991 Jun 09 12:33:10 PM PDT 24 Jun 09 12:33:12 PM PDT 24 240419699 ps
T900 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1065346340 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 99475746 ps
T901 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3910901427 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 130207490 ps
T902 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.265529800 Jun 09 12:33:15 PM PDT 24 Jun 09 12:33:17 PM PDT 24 206054148 ps
T903 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.138537811 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:16 PM PDT 24 60517534 ps
T904 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3262331143 Jun 09 12:33:15 PM PDT 24 Jun 09 12:33:16 PM PDT 24 45626127 ps
T905 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1786999411 Jun 09 12:33:19 PM PDT 24 Jun 09 12:33:21 PM PDT 24 275191527 ps
T906 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470554191 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:17 PM PDT 24 59132261 ps
T907 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3062058204 Jun 09 12:33:11 PM PDT 24 Jun 09 12:33:13 PM PDT 24 119671212 ps
T908 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1428504628 Jun 09 12:33:15 PM PDT 24 Jun 09 12:33:17 PM PDT 24 96670495 ps
T909 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1319475560 Jun 09 12:33:22 PM PDT 24 Jun 09 12:33:24 PM PDT 24 256289584 ps
T910 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3083995131 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 240462373 ps
T911 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2790502005 Jun 09 12:33:20 PM PDT 24 Jun 09 12:33:21 PM PDT 24 59645970 ps
T912 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.689471347 Jun 09 12:33:20 PM PDT 24 Jun 09 12:33:21 PM PDT 24 114521348 ps
T913 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.592255766 Jun 09 12:33:24 PM PDT 24 Jun 09 12:33:25 PM PDT 24 52977833 ps
T914 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.219490479 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:18 PM PDT 24 40249020 ps
T915 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1631891055 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 54083619 ps
T916 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.481334724 Jun 09 12:33:15 PM PDT 24 Jun 09 12:33:17 PM PDT 24 47622547 ps
T917 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.232216200 Jun 09 12:33:25 PM PDT 24 Jun 09 12:33:27 PM PDT 24 149423218 ps
T918 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3259926248 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:23 PM PDT 24 148160627 ps
T919 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4117333758 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 27500689 ps
T920 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1818187507 Jun 09 12:33:10 PM PDT 24 Jun 09 12:33:11 PM PDT 24 94251867 ps
T921 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1496664716 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 279793590 ps
T922 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1884339031 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 200357231 ps
T923 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1444252285 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:18 PM PDT 24 190894888 ps
T924 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.709889592 Jun 09 12:33:22 PM PDT 24 Jun 09 12:33:24 PM PDT 24 48041553 ps
T925 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3036100668 Jun 09 12:33:12 PM PDT 24 Jun 09 12:33:14 PM PDT 24 258841700 ps
T926 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2908816152 Jun 09 12:33:11 PM PDT 24 Jun 09 12:33:12 PM PDT 24 137744377 ps
T927 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3678374493 Jun 09 12:33:18 PM PDT 24 Jun 09 12:33:20 PM PDT 24 407810753 ps
T928 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2984218275 Jun 09 12:33:21 PM PDT 24 Jun 09 12:33:23 PM PDT 24 242603588 ps
T929 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2137731490 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:17 PM PDT 24 156706220 ps
T930 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3407401440 Jun 09 12:33:04 PM PDT 24 Jun 09 12:33:05 PM PDT 24 184323274 ps
T931 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.942626561 Jun 09 12:33:11 PM PDT 24 Jun 09 12:33:13 PM PDT 24 150053582 ps
T932 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.551433699 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:14 PM PDT 24 43940044 ps
T933 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.124855474 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:18 PM PDT 24 43580645 ps
T934 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.239716654 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:18 PM PDT 24 783450862 ps
T935 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3419643042 Jun 09 12:33:20 PM PDT 24 Jun 09 12:33:22 PM PDT 24 161173907 ps
T936 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1479440360 Jun 09 12:33:21 PM PDT 24 Jun 09 12:33:27 PM PDT 24 42860692 ps
T937 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2694850193 Jun 09 12:33:16 PM PDT 24 Jun 09 12:33:17 PM PDT 24 1089684269 ps
T938 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.530856474 Jun 09 12:33:10 PM PDT 24 Jun 09 12:33:12 PM PDT 24 47828136 ps
T939 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2337248455 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 232856014 ps
T940 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1889090880 Jun 09 12:33:13 PM PDT 24 Jun 09 12:33:15 PM PDT 24 244176310 ps
T941 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3868502871 Jun 09 12:33:17 PM PDT 24 Jun 09 12:33:19 PM PDT 24 58083314 ps
T942 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.828739017 Jun 09 12:33:14 PM PDT 24 Jun 09 12:33:16 PM PDT 24 54185605 ps

Test location /workspace/coverage/default/49.gpio_full_random.419138764
Short name T24
Test name
Test status
Simulation time 98025372 ps
CPU time 0.87 seconds
Started Jun 09 01:37:18 PM PDT 24
Finished Jun 09 01:37:19 PM PDT 24
Peak memory 196956 kb
Host smart-698427a8-34bd-45ca-a12d-91960e36ee2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419138764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.419138764
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3636236741
Short name T29
Test name
Test status
Simulation time 172149791 ps
CPU time 3.51 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:30 PM PDT 24
Peak memory 198056 kb
Host smart-259d67c1-fa12-4aa5-a010-db97b0f65cd4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636236741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3636236741
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.514846017
Short name T30
Test name
Test status
Simulation time 787046488438 ps
CPU time 1890.53 seconds
Started Jun 09 01:36:22 PM PDT 24
Finished Jun 09 02:07:53 PM PDT 24
Peak memory 198272 kb
Host smart-6d152464-94f4-4aea-9566-50dcd0c06820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=514846017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.514846017
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2010685277
Short name T1
Test name
Test status
Simulation time 1419834994 ps
CPU time 3.86 seconds
Started Jun 09 01:34:58 PM PDT 24
Finished Jun 09 01:35:02 PM PDT 24
Peak memory 198180 kb
Host smart-99e70da6-1e3d-4b52-bfb3-7f3cd104c638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010685277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2010685277
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1255724332
Short name T37
Test name
Test status
Simulation time 327174838 ps
CPU time 0.95 seconds
Started Jun 09 01:34:12 PM PDT 24
Finished Jun 09 01:34:14 PM PDT 24
Peak memory 215004 kb
Host smart-9b78d9cf-affc-4eac-beee-efee8892defd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255724332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1255724332
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1961944227
Short name T82
Test name
Test status
Simulation time 18640852 ps
CPU time 0.65 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:50 PM PDT 24
Peak memory 194464 kb
Host smart-4a837759-ed08-4256-ae8c-5053e13f4c8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961944227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1961944227
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1225849271
Short name T43
Test name
Test status
Simulation time 209875995 ps
CPU time 1.51 seconds
Started Jun 09 12:42:16 PM PDT 24
Finished Jun 09 12:42:17 PM PDT 24
Peak memory 197924 kb
Host smart-2e5a0e8a-7ef5-48bb-8980-d5ec16782c48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225849271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1225849271
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.688252547
Short name T11
Test name
Test status
Simulation time 41846635 ps
CPU time 0.55 seconds
Started Jun 09 01:34:16 PM PDT 24
Finished Jun 09 01:34:17 PM PDT 24
Peak memory 193956 kb
Host smart-bff04c89-9213-4bcd-b63a-2683631a20db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688252547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.688252547
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3689267928
Short name T67
Test name
Test status
Simulation time 12676732 ps
CPU time 0.62 seconds
Started Jun 09 12:42:22 PM PDT 24
Finished Jun 09 12:42:23 PM PDT 24
Peak memory 194944 kb
Host smart-0ccda356-d9ae-4854-8746-be2c85c53234
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689267928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3689267928
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3461680636
Short name T86
Test name
Test status
Simulation time 27277843 ps
CPU time 0.82 seconds
Started Jun 09 12:42:20 PM PDT 24
Finished Jun 09 12:42:21 PM PDT 24
Peak memory 196320 kb
Host smart-34b63215-74bf-4b30-b6ed-d1d2b2b43fc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461680636 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3461680636
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4210604556
Short name T39
Test name
Test status
Simulation time 102506600 ps
CPU time 1.21 seconds
Started Jun 09 12:42:41 PM PDT 24
Finished Jun 09 12:42:43 PM PDT 24
Peak memory 197932 kb
Host smart-8e869d8e-53d4-4e5c-86e0-70687057e4a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210604556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4210604556
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1482770159
Short name T775
Test name
Test status
Simulation time 22058042 ps
CPU time 0.66 seconds
Started Jun 09 12:42:16 PM PDT 24
Finished Jun 09 12:42:17 PM PDT 24
Peak memory 194300 kb
Host smart-02b69373-f82c-4c1a-8122-5229891cf7f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482770159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1482770159
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2549771587
Short name T842
Test name
Test status
Simulation time 1348327360 ps
CPU time 3.51 seconds
Started Jun 09 12:42:23 PM PDT 24
Finished Jun 09 12:42:27 PM PDT 24
Peak memory 197844 kb
Host smart-20887a40-3a05-4dcc-8a5c-3cefed4d8ad2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549771587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2549771587
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.968984437
Short name T820
Test name
Test status
Simulation time 44461036 ps
CPU time 0.66 seconds
Started Jun 09 12:42:19 PM PDT 24
Finished Jun 09 12:42:20 PM PDT 24
Peak memory 195000 kb
Host smart-26391c67-0d8c-4e62-b47b-a5372c206e6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968984437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.968984437
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2015098139
Short name T806
Test name
Test status
Simulation time 31764789 ps
CPU time 1.35 seconds
Started Jun 09 12:42:16 PM PDT 24
Finished Jun 09 12:42:17 PM PDT 24
Peak memory 197988 kb
Host smart-d7509fef-e9b3-45ea-999a-1c1e85ccf3af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015098139 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2015098139
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3979246946
Short name T749
Test name
Test status
Simulation time 37505768 ps
CPU time 0.57 seconds
Started Jun 09 12:42:14 PM PDT 24
Finished Jun 09 12:42:14 PM PDT 24
Peak memory 195076 kb
Host smart-dd8d06a4-5ac4-409d-b5cf-45d9eaa196ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979246946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3979246946
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3449582788
Short name T840
Test name
Test status
Simulation time 82092781 ps
CPU time 0.63 seconds
Started Jun 09 12:42:14 PM PDT 24
Finished Jun 09 12:42:15 PM PDT 24
Peak memory 193568 kb
Host smart-c80cfab1-de86-4364-b524-cbf5a54390ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449582788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3449582788
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3158661236
Short name T797
Test name
Test status
Simulation time 73236942 ps
CPU time 0.91 seconds
Started Jun 09 12:42:15 PM PDT 24
Finished Jun 09 12:42:16 PM PDT 24
Peak memory 196976 kb
Host smart-ba68f87b-801c-47ef-84f2-8c014e85619b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158661236 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3158661236
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1259764556
Short name T795
Test name
Test status
Simulation time 65067598 ps
CPU time 1.51 seconds
Started Jun 09 12:42:17 PM PDT 24
Finished Jun 09 12:42:19 PM PDT 24
Peak memory 197904 kb
Host smart-32675cfe-eb70-43fa-ab04-d43722d9a971
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259764556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1259764556
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3127722787
Short name T102
Test name
Test status
Simulation time 16352441 ps
CPU time 0.67 seconds
Started Jun 09 12:42:21 PM PDT 24
Finished Jun 09 12:42:22 PM PDT 24
Peak memory 194720 kb
Host smart-29094e50-bbc2-4dfd-a8cc-2ac1789cffe6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127722787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3127722787
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.427690343
Short name T77
Test name
Test status
Simulation time 2630984937 ps
CPU time 3.58 seconds
Started Jun 09 12:42:19 PM PDT 24
Finished Jun 09 12:42:23 PM PDT 24
Peak memory 197968 kb
Host smart-bf9592d2-7ed2-4fdb-bc49-5c17df2d7f6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427690343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.427690343
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1692888275
Short name T778
Test name
Test status
Simulation time 18238284 ps
CPU time 0.69 seconds
Started Jun 09 12:42:20 PM PDT 24
Finished Jun 09 12:42:21 PM PDT 24
Peak memory 194876 kb
Host smart-51874464-4281-477a-a59a-1af496d8847e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692888275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1692888275
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.415174311
Short name T731
Test name
Test status
Simulation time 33759965 ps
CPU time 0.95 seconds
Started Jun 09 12:42:17 PM PDT 24
Finished Jun 09 12:42:18 PM PDT 24
Peak memory 197892 kb
Host smart-1ab746ae-d377-4c94-b04b-2bde5f94868a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415174311 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.415174311
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1144035909
Short name T772
Test name
Test status
Simulation time 34233283 ps
CPU time 0.6 seconds
Started Jun 09 12:42:21 PM PDT 24
Finished Jun 09 12:42:22 PM PDT 24
Peak memory 193564 kb
Host smart-ac257ada-2344-4b6a-a1ec-422eedc4dc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144035909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1144035909
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2896165142
Short name T746
Test name
Test status
Simulation time 488370856 ps
CPU time 2.65 seconds
Started Jun 09 12:42:18 PM PDT 24
Finished Jun 09 12:42:21 PM PDT 24
Peak memory 198236 kb
Host smart-3eb02842-4d90-48f1-8630-eac0182fe1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896165142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2896165142
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3315878830
Short name T42
Test name
Test status
Simulation time 279023113 ps
CPU time 1.5 seconds
Started Jun 09 12:42:20 PM PDT 24
Finished Jun 09 12:42:22 PM PDT 24
Peak memory 197956 kb
Host smart-5f345fa3-441c-4f82-87f0-70e87ffd7160
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315878830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3315878830
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2137737091
Short name T727
Test name
Test status
Simulation time 33153589 ps
CPU time 1.62 seconds
Started Jun 09 12:42:39 PM PDT 24
Finished Jun 09 12:42:41 PM PDT 24
Peak memory 198076 kb
Host smart-c342dd53-2eeb-4dcf-8b56-0861b3ffe8e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137737091 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2137737091
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3558903577
Short name T76
Test name
Test status
Simulation time 44235054 ps
CPU time 0.66 seconds
Started Jun 09 12:42:39 PM PDT 24
Finished Jun 09 12:42:40 PM PDT 24
Peak memory 194744 kb
Host smart-adb88575-a92e-42ea-9bfd-41b4b5a0f1af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558903577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3558903577
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3494554166
Short name T729
Test name
Test status
Simulation time 123675622 ps
CPU time 0.56 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 194240 kb
Host smart-07208464-1eea-4488-b91a-a3db56935e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494554166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3494554166
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.135395907
Short name T87
Test name
Test status
Simulation time 40871825 ps
CPU time 0.88 seconds
Started Jun 09 12:42:42 PM PDT 24
Finished Jun 09 12:42:43 PM PDT 24
Peak memory 196372 kb
Host smart-8073d9f2-a089-4d2e-813e-086f059a6247
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135395907 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.135395907
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1434546188
Short name T751
Test name
Test status
Simulation time 104648963 ps
CPU time 1.41 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 197892 kb
Host smart-54410c50-ac78-46d1-a654-16df188233a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434546188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1434546188
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1801497578
Short name T44
Test name
Test status
Simulation time 377151306 ps
CPU time 1.35 seconds
Started Jun 09 12:42:38 PM PDT 24
Finished Jun 09 12:42:40 PM PDT 24
Peak memory 197876 kb
Host smart-7e9341fa-b0e5-4e50-8817-f465fdde7dc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801497578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1801497578
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2580783564
Short name T794
Test name
Test status
Simulation time 28000845 ps
CPU time 1.54 seconds
Started Jun 09 12:42:44 PM PDT 24
Finished Jun 09 12:42:46 PM PDT 24
Peak memory 198036 kb
Host smart-3767d106-d44e-41e5-ae41-48ba23b3cfcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580783564 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2580783564
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.412629109
Short name T69
Test name
Test status
Simulation time 17121957 ps
CPU time 0.62 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 195052 kb
Host smart-92e36e17-219a-4b8d-9ef1-ce5e6b4a5d04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412629109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.412629109
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.782035248
Short name T760
Test name
Test status
Simulation time 12754131 ps
CPU time 0.59 seconds
Started Jun 09 12:42:42 PM PDT 24
Finished Jun 09 12:42:43 PM PDT 24
Peak memory 193572 kb
Host smart-1f709d9a-673a-41a5-b6db-ebda60a54a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782035248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.782035248
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3409589820
Short name T791
Test name
Test status
Simulation time 46612779 ps
CPU time 0.65 seconds
Started Jun 09 12:42:46 PM PDT 24
Finished Jun 09 12:42:47 PM PDT 24
Peak memory 194744 kb
Host smart-6f0def89-cdb6-4ce1-854f-da787fc227e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409589820 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3409589820
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1835675650
Short name T789
Test name
Test status
Simulation time 560572178 ps
CPU time 2.51 seconds
Started Jun 09 12:42:42 PM PDT 24
Finished Jun 09 12:42:45 PM PDT 24
Peak memory 197880 kb
Host smart-1939cc14-4157-4cea-8ec1-89919089a242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835675650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1835675650
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3054624350
Short name T35
Test name
Test status
Simulation time 80871430 ps
CPU time 1.19 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 197940 kb
Host smart-4ae52190-4df0-406d-bcb1-bfb89e5e19ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054624350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3054624350
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3183643954
Short name T788
Test name
Test status
Simulation time 40507701 ps
CPU time 0.82 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 197884 kb
Host smart-d3da58f3-ea61-4bb9-a6ea-c177e538a4a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183643954 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3183643954
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1217011581
Short name T793
Test name
Test status
Simulation time 44763565 ps
CPU time 0.59 seconds
Started Jun 09 12:42:44 PM PDT 24
Finished Jun 09 12:42:45 PM PDT 24
Peak memory 193524 kb
Host smart-f307beeb-33fe-417b-bdfd-858b3714fed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217011581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1217011581
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3417235319
Short name T758
Test name
Test status
Simulation time 173618521 ps
CPU time 0.72 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:44 PM PDT 24
Peak memory 196228 kb
Host smart-be330b00-624e-4c57-9839-63876d0bdaa1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417235319 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3417235319
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1728538564
Short name T799
Test name
Test status
Simulation time 126478317 ps
CPU time 1.97 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:46 PM PDT 24
Peak memory 197948 kb
Host smart-b397ec91-c2a2-4ba3-b3e7-bc552b860669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728538564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1728538564
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1692965376
Short name T835
Test name
Test status
Simulation time 203905732 ps
CPU time 1.23 seconds
Started Jun 09 12:42:42 PM PDT 24
Finished Jun 09 12:42:43 PM PDT 24
Peak memory 197952 kb
Host smart-77612112-b6f1-4c23-be1a-97394a7e3e89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692965376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1692965376
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.746993755
Short name T743
Test name
Test status
Simulation time 28013269 ps
CPU time 0.89 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:45 PM PDT 24
Peak memory 197836 kb
Host smart-35466a51-34f1-41a3-ae9a-bdd3641f4dbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746993755 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.746993755
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1231901507
Short name T81
Test name
Test status
Simulation time 14148664 ps
CPU time 0.59 seconds
Started Jun 09 12:42:42 PM PDT 24
Finished Jun 09 12:42:43 PM PDT 24
Peak memory 193568 kb
Host smart-fc6b7f95-c179-4418-8a39-d0a72c2cfd69
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231901507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1231901507
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.815165176
Short name T738
Test name
Test status
Simulation time 14013355 ps
CPU time 0.59 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:50 PM PDT 24
Peak memory 193560 kb
Host smart-90d7770a-e96e-4662-b8f3-4ad96beaa34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815165176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.815165176
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4141502682
Short name T74
Test name
Test status
Simulation time 73646923 ps
CPU time 0.94 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:51 PM PDT 24
Peak memory 196924 kb
Host smart-fdd3a46e-b411-439a-85de-6130a19c4876
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141502682 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.4141502682
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.809660010
Short name T838
Test name
Test status
Simulation time 28407415 ps
CPU time 1.54 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:51 PM PDT 24
Peak memory 197784 kb
Host smart-f4baacfc-84bf-43d1-85d5-829325559b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809660010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.809660010
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.22478502
Short name T756
Test name
Test status
Simulation time 517077090 ps
CPU time 1.17 seconds
Started Jun 09 12:42:43 PM PDT 24
Finished Jun 09 12:42:45 PM PDT 24
Peak memory 197948 kb
Host smart-c4035083-c361-46b0-ae55-0cff37f5b436
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22478502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.gpio_tl_intg_err.22478502
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.569463240
Short name T786
Test name
Test status
Simulation time 21191054 ps
CPU time 0.95 seconds
Started Jun 09 12:42:47 PM PDT 24
Finished Jun 09 12:42:48 PM PDT 24
Peak memory 198156 kb
Host smart-46444976-13d1-4c94-b2d1-cbe522eab434
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569463240 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.569463240
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3387845290
Short name T783
Test name
Test status
Simulation time 14335208 ps
CPU time 0.63 seconds
Started Jun 09 12:42:44 PM PDT 24
Finished Jun 09 12:42:45 PM PDT 24
Peak memory 194696 kb
Host smart-dd258ea0-6c9d-40bb-8229-a1a54e9512bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387845290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3387845290
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1637035357
Short name T728
Test name
Test status
Simulation time 41240563 ps
CPU time 0.58 seconds
Started Jun 09 12:42:50 PM PDT 24
Finished Jun 09 12:42:51 PM PDT 24
Peak memory 194220 kb
Host smart-305718b5-902c-40ce-83ef-076bbec2fd19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637035357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1637035357
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2703291621
Short name T88
Test name
Test status
Simulation time 20619094 ps
CPU time 0.75 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 196780 kb
Host smart-ac25e39f-41d6-42ae-b01c-4ac78cc043c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703291621 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2703291621
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2231512893
Short name T733
Test name
Test status
Simulation time 310518892 ps
CPU time 2.56 seconds
Started Jun 09 12:42:47 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 197956 kb
Host smart-8e445d66-ea3e-4ef6-9d84-4b9d3521e8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231512893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2231512893
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.554297683
Short name T831
Test name
Test status
Simulation time 133444878 ps
CPU time 0.87 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 196872 kb
Host smart-4b8148a9-7ec0-4f54-8eeb-822d38fc5476
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554297683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.554297683
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1468649854
Short name T801
Test name
Test status
Simulation time 340067466 ps
CPU time 1.07 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 197884 kb
Host smart-a8074474-dc4c-41ef-9029-1ff614c880c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468649854 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1468649854
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2336414408
Short name T70
Test name
Test status
Simulation time 88382309 ps
CPU time 0.59 seconds
Started Jun 09 12:42:51 PM PDT 24
Finished Jun 09 12:42:53 PM PDT 24
Peak memory 194260 kb
Host smart-b682930a-61b5-4dbb-85ec-c23043d15d38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336414408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2336414408
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2548851606
Short name T747
Test name
Test status
Simulation time 20717606 ps
CPU time 0.63 seconds
Started Jun 09 12:42:50 PM PDT 24
Finished Jun 09 12:42:51 PM PDT 24
Peak memory 193656 kb
Host smart-0b8be998-8a7e-4e5c-945d-b0344c4b16b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548851606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2548851606
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1557190108
Short name T75
Test name
Test status
Simulation time 43925102 ps
CPU time 0.75 seconds
Started Jun 09 12:42:46 PM PDT 24
Finished Jun 09 12:42:47 PM PDT 24
Peak memory 195576 kb
Host smart-1581c29c-273b-4969-b2d3-d784b47348b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557190108 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1557190108
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1197401503
Short name T790
Test name
Test status
Simulation time 54742835 ps
CPU time 3.02 seconds
Started Jun 09 12:42:51 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 197920 kb
Host smart-524688eb-f2f9-4eec-b375-998e77478fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197401503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1197401503
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2072117648
Short name T837
Test name
Test status
Simulation time 129023717 ps
CPU time 0.9 seconds
Started Jun 09 12:42:50 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 197816 kb
Host smart-9d12db3c-f004-44e3-a002-e7cb92f3a0f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072117648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2072117648
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1023736311
Short name T748
Test name
Test status
Simulation time 18470836 ps
CPU time 0.66 seconds
Started Jun 09 12:42:46 PM PDT 24
Finished Jun 09 12:42:47 PM PDT 24
Peak memory 196744 kb
Host smart-2796daa6-bb1f-47bc-a69e-ee680aa12636
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023736311 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1023736311
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.669718357
Short name T764
Test name
Test status
Simulation time 103593057 ps
CPU time 0.63 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 194316 kb
Host smart-4cadbe2c-a9d9-4bf3-9cbe-a955f3864117
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669718357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.669718357
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2593929473
Short name T765
Test name
Test status
Simulation time 35468167 ps
CPU time 0.59 seconds
Started Jun 09 12:42:51 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 193548 kb
Host smart-db7d015e-103d-40cf-8c0c-2fdd54b394db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593929473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2593929473
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3295295896
Short name T785
Test name
Test status
Simulation time 116125832 ps
CPU time 0.83 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 197068 kb
Host smart-73171caa-f69a-4a76-b5c8-52e3f14e68ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295295896 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3295295896
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.705236935
Short name T841
Test name
Test status
Simulation time 954079948 ps
CPU time 2.32 seconds
Started Jun 09 12:42:50 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 197900 kb
Host smart-62136feb-7994-4c96-b22f-240d55cd7c59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705236935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.705236935
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1756248572
Short name T103
Test name
Test status
Simulation time 143329095 ps
CPU time 1.17 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 197584 kb
Host smart-e9383ee6-969f-4990-90f6-f9ce21b60e02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756248572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1756248572
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2304812944
Short name T771
Test name
Test status
Simulation time 123831095 ps
CPU time 0.89 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 197932 kb
Host smart-619dfee6-833b-4b2b-8990-891b5eb4363d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304812944 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2304812944
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.854870059
Short name T73
Test name
Test status
Simulation time 68943392 ps
CPU time 0.63 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:50 PM PDT 24
Peak memory 194620 kb
Host smart-3190c50b-b3c1-4a96-8d87-0b2749fcff03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854870059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.854870059
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2104208281
Short name T721
Test name
Test status
Simulation time 63217644 ps
CPU time 0.63 seconds
Started Jun 09 12:42:51 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 193644 kb
Host smart-ed9ae128-5e18-457c-b020-b9c7d9439bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104208281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2104208281
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3515603586
Short name T776
Test name
Test status
Simulation time 67611339 ps
CPU time 0.74 seconds
Started Jun 09 12:42:47 PM PDT 24
Finished Jun 09 12:42:48 PM PDT 24
Peak memory 196012 kb
Host smart-2b294d7f-65f9-48ab-9ba4-8fdf10b23e26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515603586 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3515603586
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3826991745
Short name T819
Test name
Test status
Simulation time 47401877 ps
CPU time 2.25 seconds
Started Jun 09 12:42:51 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 197936 kb
Host smart-e01176c0-48e2-4838-850f-78521f8e5764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826991745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3826991745
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2329874317
Short name T807
Test name
Test status
Simulation time 293513183 ps
CPU time 1.16 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 197568 kb
Host smart-7a85b751-936e-4bcc-90e3-13d3be51ce5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329874317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2329874317
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3502758709
Short name T744
Test name
Test status
Simulation time 23939389 ps
CPU time 0.81 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 197804 kb
Host smart-ef76f1dc-7d7a-428e-81e8-5d497af7692e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502758709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3502758709
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3712921271
Short name T829
Test name
Test status
Simulation time 14373997 ps
CPU time 0.6 seconds
Started Jun 09 12:42:46 PM PDT 24
Finished Jun 09 12:42:46 PM PDT 24
Peak memory 194920 kb
Host smart-38bbde05-dc46-4080-8a9e-2b8a7e4aa4a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712921271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3712921271
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3884889578
Short name T803
Test name
Test status
Simulation time 13002397 ps
CPU time 0.6 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:50 PM PDT 24
Peak memory 194248 kb
Host smart-3279ac2f-d6c8-4ead-85f1-47105045ccd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884889578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3884889578
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.617368732
Short name T750
Test name
Test status
Simulation time 367753722 ps
CPU time 0.7 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:50 PM PDT 24
Peak memory 194552 kb
Host smart-87cb4cb8-82d4-4da5-bfa3-5469a77bb1fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617368732 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.617368732
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.738409639
Short name T814
Test name
Test status
Simulation time 130058508 ps
CPU time 1.94 seconds
Started Jun 09 12:42:50 PM PDT 24
Finished Jun 09 12:42:53 PM PDT 24
Peak memory 197956 kb
Host smart-8404e24f-26ed-459d-9523-e9570d97bdd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738409639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.738409639
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.938727812
Short name T734
Test name
Test status
Simulation time 42888239 ps
CPU time 0.89 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:50 PM PDT 24
Peak memory 197832 kb
Host smart-5b301faa-f639-470a-b22c-3656cf8c6fb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938727812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.938727812
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3185729434
Short name T757
Test name
Test status
Simulation time 25008208 ps
CPU time 0.79 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 197928 kb
Host smart-42c62af6-6679-4294-be95-1567f5f77173
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185729434 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3185729434
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.612405090
Short name T80
Test name
Test status
Simulation time 45016717 ps
CPU time 0.63 seconds
Started Jun 09 12:42:48 PM PDT 24
Finished Jun 09 12:42:49 PM PDT 24
Peak memory 195580 kb
Host smart-bd22afc2-cc06-409f-a653-4ee81b8a40e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612405090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.612405090
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3898308749
Short name T817
Test name
Test status
Simulation time 31168640 ps
CPU time 0.59 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 193576 kb
Host smart-690cf3cb-da83-4a15-b4d4-a81c1a1ee2b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898308749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3898308749
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3389484715
Short name T774
Test name
Test status
Simulation time 772192124 ps
CPU time 0.86 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 196088 kb
Host smart-4b927dbb-209b-4f2b-a580-f98fdb8efa85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389484715 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3389484715
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3626079586
Short name T833
Test name
Test status
Simulation time 309711886 ps
CPU time 2.85 seconds
Started Jun 09 12:42:49 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 197948 kb
Host smart-84846a55-de7e-4b6b-8971-c1450cb827c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626079586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3626079586
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.63686462
Short name T34
Test name
Test status
Simulation time 78020719 ps
CPU time 1.21 seconds
Started Jun 09 12:42:50 PM PDT 24
Finished Jun 09 12:42:52 PM PDT 24
Peak memory 197952 kb
Host smart-aef20725-e973-470e-8614-a7667982a1d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63686462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.gpio_tl_intg_err.63686462
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3362561422
Short name T816
Test name
Test status
Simulation time 59768805 ps
CPU time 0.89 seconds
Started Jun 09 12:42:22 PM PDT 24
Finished Jun 09 12:42:23 PM PDT 24
Peak memory 196132 kb
Host smart-2dbcf955-c8f2-4665-83b3-7d94b9df6900
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362561422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3362561422
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2591009555
Short name T770
Test name
Test status
Simulation time 1675737469 ps
CPU time 3.38 seconds
Started Jun 09 12:42:23 PM PDT 24
Finished Jun 09 12:42:27 PM PDT 24
Peak memory 196644 kb
Host smart-9aa7b789-ad18-4bdd-bc59-a54997a6c3fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591009555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2591009555
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1818270078
Short name T762
Test name
Test status
Simulation time 18986272 ps
CPU time 0.64 seconds
Started Jun 09 12:42:24 PM PDT 24
Finished Jun 09 12:42:25 PM PDT 24
Peak memory 194744 kb
Host smart-5ab32f8e-ceed-4869-a1c7-6d19185257f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818270078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1818270078
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1285991768
Short name T741
Test name
Test status
Simulation time 79493968 ps
CPU time 1.06 seconds
Started Jun 09 12:42:26 PM PDT 24
Finished Jun 09 12:42:28 PM PDT 24
Peak memory 197924 kb
Host smart-b23903e7-2df4-4825-a318-c29c71c8c786
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285991768 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1285991768
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.702973832
Short name T68
Test name
Test status
Simulation time 39660212 ps
CPU time 0.61 seconds
Started Jun 09 12:42:19 PM PDT 24
Finished Jun 09 12:42:19 PM PDT 24
Peak memory 194940 kb
Host smart-9f91d9d4-e829-46e4-9d59-242a04cc9e11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702973832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.702973832
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4248804050
Short name T809
Test name
Test status
Simulation time 30411000 ps
CPU time 0.6 seconds
Started Jun 09 12:42:24 PM PDT 24
Finished Jun 09 12:42:25 PM PDT 24
Peak memory 193604 kb
Host smart-6610d7bd-fb89-4be0-80e4-b5a1ecbc04fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248804050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4248804050
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4228679179
Short name T777
Test name
Test status
Simulation time 22559974 ps
CPU time 0.73 seconds
Started Jun 09 12:42:21 PM PDT 24
Finished Jun 09 12:42:22 PM PDT 24
Peak memory 194740 kb
Host smart-50406765-2918-477a-9423-3a40a38f7b9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228679179 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4228679179
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2260618399
Short name T805
Test name
Test status
Simulation time 229179752 ps
CPU time 2.42 seconds
Started Jun 09 12:42:24 PM PDT 24
Finished Jun 09 12:42:27 PM PDT 24
Peak memory 197924 kb
Host smart-1c5cff5d-fe7d-42ad-ae33-fb9740519115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260618399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2260618399
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2357938414
Short name T41
Test name
Test status
Simulation time 234265596 ps
CPU time 1.33 seconds
Started Jun 09 12:42:25 PM PDT 24
Finished Jun 09 12:42:27 PM PDT 24
Peak memory 197952 kb
Host smart-c195c043-19d8-4409-89a7-7d3fc27247b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357938414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2357938414
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1513789024
Short name T769
Test name
Test status
Simulation time 46167318 ps
CPU time 0.6 seconds
Started Jun 09 12:42:55 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 193552 kb
Host smart-de972551-4916-4157-b47f-e479713df411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513789024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1513789024
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2166782138
Short name T781
Test name
Test status
Simulation time 11743239 ps
CPU time 0.58 seconds
Started Jun 09 12:42:52 PM PDT 24
Finished Jun 09 12:42:53 PM PDT 24
Peak memory 193536 kb
Host smart-5c724772-f381-453c-88c7-091769a062a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166782138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2166782138
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2862149334
Short name T717
Test name
Test status
Simulation time 13649129 ps
CPU time 0.6 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 194248 kb
Host smart-e87623b4-22be-42f1-8a7e-aa5f172bae02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862149334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2862149334
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1455175464
Short name T780
Test name
Test status
Simulation time 87108800 ps
CPU time 0.57 seconds
Started Jun 09 12:42:52 PM PDT 24
Finished Jun 09 12:42:53 PM PDT 24
Peak memory 194256 kb
Host smart-1f40ee13-a8a8-4917-bf25-b76bfefd28ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455175464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1455175464
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2329312189
Short name T824
Test name
Test status
Simulation time 14519741 ps
CPU time 0.61 seconds
Started Jun 09 12:42:56 PM PDT 24
Finished Jun 09 12:42:57 PM PDT 24
Peak memory 193588 kb
Host smart-0ede682f-30aa-4c04-930c-2d091132af4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329312189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2329312189
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2155652194
Short name T766
Test name
Test status
Simulation time 18172075 ps
CPU time 0.61 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 193600 kb
Host smart-1a4d198b-e11d-4e63-a87b-d62540836fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155652194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2155652194
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2922639871
Short name T792
Test name
Test status
Simulation time 17326303 ps
CPU time 0.59 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 193580 kb
Host smart-27926b55-2711-4144-9f97-2a48b9ce3ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922639871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2922639871
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3488503565
Short name T737
Test name
Test status
Simulation time 14573294 ps
CPU time 0.58 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 193564 kb
Host smart-c6bf82bf-4945-4a38-9c55-b99190887afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488503565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3488503565
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1339150873
Short name T834
Test name
Test status
Simulation time 40310936 ps
CPU time 0.68 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 193624 kb
Host smart-b013d901-ac98-4576-bc90-57cf960eed5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339150873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1339150873
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3959642022
Short name T718
Test name
Test status
Simulation time 17502027 ps
CPU time 0.61 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 193624 kb
Host smart-17185982-f85e-4663-8ea0-d6a372d6b8c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959642022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3959642022
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.385034006
Short name T798
Test name
Test status
Simulation time 66692373 ps
CPU time 0.87 seconds
Started Jun 09 12:42:23 PM PDT 24
Finished Jun 09 12:42:24 PM PDT 24
Peak memory 196060 kb
Host smart-77384573-c7f9-42ab-aadb-2597a5906dfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385034006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.385034006
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3605171759
Short name T779
Test name
Test status
Simulation time 110265042 ps
CPU time 2.25 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:36 PM PDT 24
Peak memory 196924 kb
Host smart-c027cd5f-aa12-44a5-bfce-838dfe9e0581
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605171759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3605171759
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4003289537
Short name T78
Test name
Test status
Simulation time 25830301 ps
CPU time 0.63 seconds
Started Jun 09 12:42:28 PM PDT 24
Finished Jun 09 12:42:29 PM PDT 24
Peak memory 194740 kb
Host smart-6a28d9cd-4aea-46f2-a496-84fe0b2a1009
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003289537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4003289537
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3980241200
Short name T800
Test name
Test status
Simulation time 61219843 ps
CPU time 0.71 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:31 PM PDT 24
Peak memory 196920 kb
Host smart-f13a883a-fdb2-4034-a190-b47201f0abcc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980241200 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3980241200
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2985192834
Short name T85
Test name
Test status
Simulation time 24097774 ps
CPU time 0.6 seconds
Started Jun 09 12:42:24 PM PDT 24
Finished Jun 09 12:42:25 PM PDT 24
Peak memory 193436 kb
Host smart-ad7f0f0e-1d64-42be-ab88-861574f69ea6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985192834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2985192834
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2350944822
Short name T730
Test name
Test status
Simulation time 31844754 ps
CPU time 0.62 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:30 PM PDT 24
Peak memory 194232 kb
Host smart-0552458e-9652-4447-96be-8da5142fe9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350944822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2350944822
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.954052637
Short name T90
Test name
Test status
Simulation time 15907925 ps
CPU time 0.79 seconds
Started Jun 09 12:42:24 PM PDT 24
Finished Jun 09 12:42:25 PM PDT 24
Peak memory 196176 kb
Host smart-f5a01592-2f19-4d5b-b2dc-7f840f8667aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954052637 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.954052637
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.198294167
Short name T723
Test name
Test status
Simulation time 64233526 ps
CPU time 3.3 seconds
Started Jun 09 12:42:32 PM PDT 24
Finished Jun 09 12:42:36 PM PDT 24
Peak memory 197884 kb
Host smart-f5469c0b-265a-4a9a-8006-49cd9bd36168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198294167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.198294167
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1957171937
Short name T825
Test name
Test status
Simulation time 835473461 ps
CPU time 1.49 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:35 PM PDT 24
Peak memory 197956 kb
Host smart-67459a37-7971-415e-aea9-a3e31c118226
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957171937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1957171937
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2226609874
Short name T759
Test name
Test status
Simulation time 42117021 ps
CPU time 0.6 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 193516 kb
Host smart-b9454981-f7c1-4dce-950d-913c37b73c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226609874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2226609874
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.482090731
Short name T726
Test name
Test status
Simulation time 14924099 ps
CPU time 0.63 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 194264 kb
Host smart-40a9fb03-c7bd-4fdb-812e-872947117796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482090731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.482090731
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4188851595
Short name T742
Test name
Test status
Simulation time 35016203 ps
CPU time 0.61 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 193580 kb
Host smart-5d763440-28e4-462a-be01-5d01370acd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188851595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4188851595
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2163030946
Short name T716
Test name
Test status
Simulation time 13886775 ps
CPU time 0.61 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 194180 kb
Host smart-388dafa0-e427-4e6f-8a31-14be01d0be85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163030946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2163030946
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2788162509
Short name T753
Test name
Test status
Simulation time 14791959 ps
CPU time 0.61 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:42:59 PM PDT 24
Peak memory 194240 kb
Host smart-89386669-d85e-4fb1-b943-f955be939ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788162509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2788162509
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1726228520
Short name T725
Test name
Test status
Simulation time 23196685 ps
CPU time 0.62 seconds
Started Jun 09 12:42:55 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 193596 kb
Host smart-e5552576-ec6e-45a4-9070-d0ca091710ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726228520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1726228520
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1360212185
Short name T732
Test name
Test status
Simulation time 47049163 ps
CPU time 0.57 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 194180 kb
Host smart-3d5bdaca-4aab-45f6-aa27-22e5b8d39ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360212185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1360212185
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2857450953
Short name T752
Test name
Test status
Simulation time 38720781 ps
CPU time 0.6 seconds
Started Jun 09 12:42:57 PM PDT 24
Finished Jun 09 12:42:58 PM PDT 24
Peak memory 193576 kb
Host smart-65a9b8aa-9cd8-4ee9-8717-079a362ef02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857450953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2857450953
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1950749343
Short name T745
Test name
Test status
Simulation time 14156940 ps
CPU time 0.58 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:42:59 PM PDT 24
Peak memory 193560 kb
Host smart-634b8a94-5e98-4429-ade0-856564fdc57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950749343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1950749343
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1637856848
Short name T811
Test name
Test status
Simulation time 18288560 ps
CPU time 0.63 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:56 PM PDT 24
Peak memory 193600 kb
Host smart-94bda511-4945-456c-b2fe-5e299f8ec719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637856848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1637856848
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1087418033
Short name T79
Test name
Test status
Simulation time 53446350 ps
CPU time 0.88 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:30 PM PDT 24
Peak memory 195976 kb
Host smart-a9691b6f-6f8f-4ad5-ba6b-6620063db93b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087418033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1087418033
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2006665836
Short name T821
Test name
Test status
Simulation time 961168902 ps
CPU time 1.57 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:31 PM PDT 24
Peak memory 198096 kb
Host smart-416a1c47-1102-48aa-8bbc-f68a08115e6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006665836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2006665836
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2025682415
Short name T796
Test name
Test status
Simulation time 21504535 ps
CPU time 0.68 seconds
Started Jun 09 12:42:28 PM PDT 24
Finished Jun 09 12:42:30 PM PDT 24
Peak memory 194812 kb
Host smart-9ad7c1f4-f345-46ba-bd85-828ef120912f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025682415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2025682415
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3202481300
Short name T755
Test name
Test status
Simulation time 22183486 ps
CPU time 1.07 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:31 PM PDT 24
Peak memory 197924 kb
Host smart-72d07e49-b8c7-4963-b7c0-80e00070af09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202481300 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3202481300
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1902208318
Short name T773
Test name
Test status
Simulation time 28372021 ps
CPU time 0.61 seconds
Started Jun 09 12:42:32 PM PDT 24
Finished Jun 09 12:42:33 PM PDT 24
Peak memory 194904 kb
Host smart-ded05670-611b-4bbc-bf19-c4a2bf5d13cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902208318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1902208318
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1058595830
Short name T828
Test name
Test status
Simulation time 35241499 ps
CPU time 0.61 seconds
Started Jun 09 12:42:31 PM PDT 24
Finished Jun 09 12:42:32 PM PDT 24
Peak memory 193560 kb
Host smart-91498a58-5c5a-4f1a-a78a-b23f64058639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058595830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1058595830
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1351371334
Short name T72
Test name
Test status
Simulation time 33334883 ps
CPU time 0.87 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:31 PM PDT 24
Peak memory 196348 kb
Host smart-e16744d1-34ce-45e2-b834-5248cedca4b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351371334 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1351371334
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2453623713
Short name T722
Test name
Test status
Simulation time 78177161 ps
CPU time 2 seconds
Started Jun 09 12:42:30 PM PDT 24
Finished Jun 09 12:42:32 PM PDT 24
Peak memory 197980 kb
Host smart-5f086645-a455-4666-8e4d-9c9ecf2f5db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453623713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2453623713
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.851368945
Short name T45
Test name
Test status
Simulation time 87825906 ps
CPU time 1.17 seconds
Started Jun 09 12:42:30 PM PDT 24
Finished Jun 09 12:42:32 PM PDT 24
Peak memory 197972 kb
Host smart-2c08ae1e-bb66-4487-8f30-dc4d938e5b4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851368945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.851368945
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3443681500
Short name T782
Test name
Test status
Simulation time 40942405 ps
CPU time 0.63 seconds
Started Jun 09 12:42:53 PM PDT 24
Finished Jun 09 12:42:54 PM PDT 24
Peak memory 193676 kb
Host smart-bd359032-1ef6-498a-9568-acac30ed62da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443681500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3443681500
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3835207660
Short name T761
Test name
Test status
Simulation time 14147756 ps
CPU time 0.58 seconds
Started Jun 09 12:42:56 PM PDT 24
Finished Jun 09 12:42:57 PM PDT 24
Peak memory 193564 kb
Host smart-3ed2e520-06e3-4220-abde-696b9fcc7dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835207660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3835207660
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.975083645
Short name T812
Test name
Test status
Simulation time 133972830 ps
CPU time 0.62 seconds
Started Jun 09 12:42:54 PM PDT 24
Finished Jun 09 12:42:55 PM PDT 24
Peak memory 193624 kb
Host smart-76e71c3e-a5be-4cf7-9e91-0c15da047565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975083645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.975083645
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1864669658
Short name T823
Test name
Test status
Simulation time 33027803 ps
CPU time 0.59 seconds
Started Jun 09 12:42:57 PM PDT 24
Finished Jun 09 12:42:58 PM PDT 24
Peak memory 194196 kb
Host smart-872a178c-0d8b-416c-8c2b-ee2e1f27a3ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864669658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1864669658
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1567588066
Short name T736
Test name
Test status
Simulation time 11261314 ps
CPU time 0.68 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:05 PM PDT 24
Peak memory 193552 kb
Host smart-738674c2-d706-4fac-aa31-065d6fc3c45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567588066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1567588066
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1065108687
Short name T719
Test name
Test status
Simulation time 59004010 ps
CPU time 0.64 seconds
Started Jun 09 12:42:57 PM PDT 24
Finished Jun 09 12:42:58 PM PDT 24
Peak memory 193896 kb
Host smart-4de71da5-f9dd-4ada-ac29-cdc71c70a369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065108687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1065108687
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3077748993
Short name T808
Test name
Test status
Simulation time 12765462 ps
CPU time 0.65 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:01 PM PDT 24
Peak memory 193648 kb
Host smart-ab0c1f99-b740-40e2-a28d-17b8a3d52d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077748993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3077748993
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.431765157
Short name T768
Test name
Test status
Simulation time 14238928 ps
CPU time 0.57 seconds
Started Jun 09 12:42:59 PM PDT 24
Finished Jun 09 12:43:00 PM PDT 24
Peak memory 194188 kb
Host smart-788b75bb-9d5c-465a-848c-43f2be100917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431765157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.431765157
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3363425701
Short name T784
Test name
Test status
Simulation time 14059761 ps
CPU time 0.59 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:42:59 PM PDT 24
Peak memory 194208 kb
Host smart-4b453c35-5c8a-43bf-83db-6c0d290ba11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363425701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3363425701
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2561851753
Short name T822
Test name
Test status
Simulation time 41624311 ps
CPU time 0.6 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:42:59 PM PDT 24
Peak memory 193588 kb
Host smart-a453af68-3f03-447e-bcc2-a90ddb9f98a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561851753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2561851753
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3930817293
Short name T720
Test name
Test status
Simulation time 61508683 ps
CPU time 1.64 seconds
Started Jun 09 12:42:32 PM PDT 24
Finished Jun 09 12:42:34 PM PDT 24
Peak memory 198004 kb
Host smart-612700c8-25bf-400d-81a6-bbeaae8d214f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930817293 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3930817293
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1212955547
Short name T84
Test name
Test status
Simulation time 33218386 ps
CPU time 0.63 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:31 PM PDT 24
Peak memory 195372 kb
Host smart-fe8e17c5-90a4-4d09-8db2-8f5a3a99b201
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212955547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1212955547
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3202923704
Short name T832
Test name
Test status
Simulation time 31569554 ps
CPU time 0.6 seconds
Started Jun 09 12:42:41 PM PDT 24
Finished Jun 09 12:42:42 PM PDT 24
Peak memory 193672 kb
Host smart-c028bdf1-cdf3-4fd4-afdc-fe71e6de8835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202923704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3202923704
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3782861499
Short name T71
Test name
Test status
Simulation time 26882539 ps
CPU time 0.76 seconds
Started Jun 09 12:42:29 PM PDT 24
Finished Jun 09 12:42:30 PM PDT 24
Peak memory 196144 kb
Host smart-2bd334d6-d9a5-48db-ad06-fff216bf6794
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782861499 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3782861499
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1629887266
Short name T715
Test name
Test status
Simulation time 33276339 ps
CPU time 1.66 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:36 PM PDT 24
Peak memory 197968 kb
Host smart-b0ee137c-eb28-4e76-bf9b-7af0bed30f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629887266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1629887266
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2913908631
Short name T40
Test name
Test status
Simulation time 298851307 ps
CPU time 1.17 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:34 PM PDT 24
Peak memory 197932 kb
Host smart-d8802426-9f32-45bf-9c8d-9f2e2844f54a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913908631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2913908631
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.257326146
Short name T830
Test name
Test status
Simulation time 59850917 ps
CPU time 0.78 seconds
Started Jun 09 12:42:34 PM PDT 24
Finished Jun 09 12:42:35 PM PDT 24
Peak memory 197920 kb
Host smart-abb10f30-a2d3-4914-8334-5f94d5784860
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257326146 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.257326146
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.105435938
Short name T83
Test name
Test status
Simulation time 16069429 ps
CPU time 0.63 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:34 PM PDT 24
Peak memory 194888 kb
Host smart-6f398d04-517c-480c-9f9a-a27604ecd3aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105435938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.105435938
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2349873428
Short name T839
Test name
Test status
Simulation time 30452112 ps
CPU time 0.64 seconds
Started Jun 09 12:42:34 PM PDT 24
Finished Jun 09 12:42:35 PM PDT 24
Peak memory 194252 kb
Host smart-6ff19c54-3ba8-4879-816e-bf29380e8f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349873428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2349873428
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1783934935
Short name T787
Test name
Test status
Simulation time 172320553 ps
CPU time 0.8 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:34 PM PDT 24
Peak memory 197016 kb
Host smart-c40503ae-b5fb-4a6b-8ac3-c10ae1b94ad7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783934935 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1783934935
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3460291292
Short name T802
Test name
Test status
Simulation time 610407998 ps
CPU time 3.35 seconds
Started Jun 09 12:42:36 PM PDT 24
Finished Jun 09 12:42:40 PM PDT 24
Peak memory 197856 kb
Host smart-f8195161-e4de-4f3f-a74c-3d91fe6ca3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460291292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3460291292
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3609296929
Short name T33
Test name
Test status
Simulation time 111281160 ps
CPU time 1.48 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:35 PM PDT 24
Peak memory 197952 kb
Host smart-63d384c7-ec33-4879-8a5d-0e91e28c0632
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609296929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3609296929
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2501389618
Short name T813
Test name
Test status
Simulation time 108710134 ps
CPU time 1.36 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:35 PM PDT 24
Peak memory 198000 kb
Host smart-24dd270f-ce2a-40d2-83fa-96dfd3a05edc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501389618 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2501389618
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2976902852
Short name T740
Test name
Test status
Simulation time 15152708 ps
CPU time 0.65 seconds
Started Jun 09 12:42:34 PM PDT 24
Finished Jun 09 12:42:35 PM PDT 24
Peak memory 194740 kb
Host smart-f071c1d8-1b28-4c9d-a9a3-6302dab789f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976902852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2976902852
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.712550425
Short name T735
Test name
Test status
Simulation time 119806693 ps
CPU time 0.65 seconds
Started Jun 09 12:42:33 PM PDT 24
Finished Jun 09 12:42:34 PM PDT 24
Peak memory 194276 kb
Host smart-8d1b6b14-2865-41bd-b3f4-a6b35d5e50a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712550425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.712550425
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1855609053
Short name T754
Test name
Test status
Simulation time 38374825 ps
CPU time 0.88 seconds
Started Jun 09 12:42:40 PM PDT 24
Finished Jun 09 12:42:41 PM PDT 24
Peak memory 197096 kb
Host smart-5f81e57d-10b8-4653-b9d1-37bdc73a6059
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855609053 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1855609053
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.6724439
Short name T724
Test name
Test status
Simulation time 36239459 ps
CPU time 2.04 seconds
Started Jun 09 12:42:34 PM PDT 24
Finished Jun 09 12:42:37 PM PDT 24
Peak memory 197920 kb
Host smart-293c9191-2f5b-4947-a8f3-f8a8af98fd96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6724439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.6724439
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3984517655
Short name T818
Test name
Test status
Simulation time 477102170 ps
CPU time 0.88 seconds
Started Jun 09 12:42:41 PM PDT 24
Finished Jun 09 12:42:42 PM PDT 24
Peak memory 197132 kb
Host smart-8c97952c-4d8c-421c-890a-52206493a7bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984517655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3984517655
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3081444476
Short name T836
Test name
Test status
Simulation time 388587459 ps
CPU time 1.33 seconds
Started Jun 09 12:42:39 PM PDT 24
Finished Jun 09 12:42:41 PM PDT 24
Peak memory 197912 kb
Host smart-5fccb897-bf16-409f-8aaf-1821345c8db1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081444476 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3081444476
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3881622800
Short name T763
Test name
Test status
Simulation time 11603822 ps
CPU time 0.56 seconds
Started Jun 09 12:42:32 PM PDT 24
Finished Jun 09 12:42:33 PM PDT 24
Peak memory 193848 kb
Host smart-9c4fc434-f56d-49be-8582-0675d4632ea7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881622800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3881622800
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1166537086
Short name T804
Test name
Test status
Simulation time 47569661 ps
CPU time 0.62 seconds
Started Jun 09 12:42:37 PM PDT 24
Finished Jun 09 12:42:38 PM PDT 24
Peak memory 193576 kb
Host smart-dc66e945-35b4-469b-becb-2bde3fad8d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166537086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1166537086
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3840323837
Short name T91
Test name
Test status
Simulation time 14932656 ps
CPU time 0.75 seconds
Started Jun 09 12:42:39 PM PDT 24
Finished Jun 09 12:42:40 PM PDT 24
Peak memory 195844 kb
Host smart-5055c5f1-ed8d-44e3-83c8-a70509f24c5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840323837 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3840323837
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3415318556
Short name T827
Test name
Test status
Simulation time 204592420 ps
CPU time 1.36 seconds
Started Jun 09 12:42:38 PM PDT 24
Finished Jun 09 12:42:39 PM PDT 24
Peak memory 197924 kb
Host smart-92018c18-73fb-4dba-a35f-1b6d8bbaec71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415318556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3415318556
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1277351688
Short name T767
Test name
Test status
Simulation time 20814451 ps
CPU time 0.69 seconds
Started Jun 09 12:42:39 PM PDT 24
Finished Jun 09 12:42:40 PM PDT 24
Peak memory 197736 kb
Host smart-2413232b-93f7-4d4d-a43b-aafb09d25d70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277351688 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1277351688
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2561408777
Short name T826
Test name
Test status
Simulation time 17947626 ps
CPU time 0.57 seconds
Started Jun 09 12:42:38 PM PDT 24
Finished Jun 09 12:42:38 PM PDT 24
Peak memory 193828 kb
Host smart-4ce83cb5-77bd-46b0-a876-e413360b250d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561408777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2561408777
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2968468084
Short name T739
Test name
Test status
Simulation time 24106121 ps
CPU time 0.65 seconds
Started Jun 09 12:42:41 PM PDT 24
Finished Jun 09 12:42:43 PM PDT 24
Peak memory 193608 kb
Host smart-49df167d-9ee3-4448-b85a-ad9280f2d7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968468084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2968468084
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1495495536
Short name T89
Test name
Test status
Simulation time 18579021 ps
CPU time 0.65 seconds
Started Jun 09 12:42:38 PM PDT 24
Finished Jun 09 12:42:39 PM PDT 24
Peak memory 195228 kb
Host smart-a3b1676d-47ce-4d03-b96a-7b29d299e066
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495495536 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1495495536
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1806543666
Short name T815
Test name
Test status
Simulation time 66057981 ps
CPU time 1.57 seconds
Started Jun 09 12:42:39 PM PDT 24
Finished Jun 09 12:42:41 PM PDT 24
Peak memory 197964 kb
Host smart-41e6d25b-454f-4477-8677-7a83cf20c005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806543666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1806543666
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1998755571
Short name T810
Test name
Test status
Simulation time 338275373 ps
CPU time 0.88 seconds
Started Jun 09 12:42:41 PM PDT 24
Finished Jun 09 12:42:42 PM PDT 24
Peak memory 197072 kb
Host smart-2c4cf763-7b97-43be-b7cb-18f615c8fdbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998755571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1998755571
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2780756411
Short name T135
Test name
Test status
Simulation time 30115138 ps
CPU time 0.58 seconds
Started Jun 09 01:34:11 PM PDT 24
Finished Jun 09 01:34:11 PM PDT 24
Peak memory 194672 kb
Host smart-f55add53-6d7c-4570-9620-553e615ebfe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780756411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2780756411
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4248095457
Short name T506
Test name
Test status
Simulation time 88670668 ps
CPU time 0.75 seconds
Started Jun 09 01:34:06 PM PDT 24
Finished Jun 09 01:34:07 PM PDT 24
Peak memory 195380 kb
Host smart-1f9866ec-158a-4fab-bb07-71114b3fa6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248095457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4248095457
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1146840336
Short name T178
Test name
Test status
Simulation time 3128272951 ps
CPU time 26.71 seconds
Started Jun 09 01:34:08 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 198092 kb
Host smart-a03e8005-9ab4-402a-9128-b1ccfdec17a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146840336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1146840336
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3934717181
Short name T378
Test name
Test status
Simulation time 111079497 ps
CPU time 0.65 seconds
Started Jun 09 01:34:07 PM PDT 24
Finished Jun 09 01:34:08 PM PDT 24
Peak memory 195388 kb
Host smart-e3b01f68-5370-4e66-bfa0-cd829136d495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934717181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3934717181
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1218440793
Short name T107
Test name
Test status
Simulation time 283176865 ps
CPU time 1.28 seconds
Started Jun 09 01:34:05 PM PDT 24
Finished Jun 09 01:34:06 PM PDT 24
Peak memory 196968 kb
Host smart-ed0b3983-e2f1-47d8-b25e-ace764c2e924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218440793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1218440793
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.441352483
Short name T556
Test name
Test status
Simulation time 106180656 ps
CPU time 1.23 seconds
Started Jun 09 01:34:05 PM PDT 24
Finished Jun 09 01:34:07 PM PDT 24
Peak memory 196744 kb
Host smart-bb95654d-fb3a-43ff-bc1d-18ddce07cca2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441352483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.441352483
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3621088283
Short name T492
Test name
Test status
Simulation time 170825889 ps
CPU time 2.25 seconds
Started Jun 09 01:34:06 PM PDT 24
Finished Jun 09 01:34:08 PM PDT 24
Peak memory 196828 kb
Host smart-ce04f4a4-880a-4e00-8f5c-1800fbc6f57a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621088283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3621088283
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4077091184
Short name T495
Test name
Test status
Simulation time 32969108 ps
CPU time 1.27 seconds
Started Jun 09 01:34:07 PM PDT 24
Finished Jun 09 01:34:08 PM PDT 24
Peak memory 195904 kb
Host smart-4c91f090-c480-4fd3-ad56-db2a13aa54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077091184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4077091184
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3099407921
Short name T512
Test name
Test status
Simulation time 29856912 ps
CPU time 0.76 seconds
Started Jun 09 01:34:06 PM PDT 24
Finished Jun 09 01:34:07 PM PDT 24
Peak memory 195496 kb
Host smart-ce89c641-1a65-4d0a-b8b3-a041cd9a5052
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099407921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3099407921
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1108661444
Short name T119
Test name
Test status
Simulation time 104770323 ps
CPU time 4.81 seconds
Started Jun 09 01:34:07 PM PDT 24
Finished Jun 09 01:34:12 PM PDT 24
Peak memory 198012 kb
Host smart-c84c0bad-d374-4f08-a0dc-b59a8c224600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108661444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1108661444
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1446175930
Short name T524
Test name
Test status
Simulation time 43248153 ps
CPU time 1.14 seconds
Started Jun 09 01:34:06 PM PDT 24
Finished Jun 09 01:34:07 PM PDT 24
Peak memory 195680 kb
Host smart-a4f09322-7d8b-41c9-a34a-571b378a532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446175930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1446175930
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.553909545
Short name T316
Test name
Test status
Simulation time 27458070 ps
CPU time 0.86 seconds
Started Jun 09 01:34:07 PM PDT 24
Finished Jun 09 01:34:08 PM PDT 24
Peak memory 196512 kb
Host smart-1f63bb58-8479-4afc-a664-6173f1c9ab47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553909545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.553909545
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.857518968
Short name T669
Test name
Test status
Simulation time 1298228201 ps
CPU time 26.72 seconds
Started Jun 09 01:34:05 PM PDT 24
Finished Jun 09 01:34:32 PM PDT 24
Peak memory 198068 kb
Host smart-cb6d71e5-7e12-40a4-a7f0-504c46431e48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857518968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.857518968
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1127735221
Short name T635
Test name
Test status
Simulation time 137713235025 ps
CPU time 1177.29 seconds
Started Jun 09 01:34:11 PM PDT 24
Finished Jun 09 01:53:49 PM PDT 24
Peak memory 198228 kb
Host smart-abf4bfed-51dc-4726-993a-bd1b9ba7567b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1127735221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1127735221
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2975374285
Short name T563
Test name
Test status
Simulation time 49110493 ps
CPU time 0.9 seconds
Started Jun 09 01:34:11 PM PDT 24
Finished Jun 09 01:34:12 PM PDT 24
Peak memory 196420 kb
Host smart-5472c859-0ec4-4088-86af-7f10ef209096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975374285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2975374285
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3434358015
Short name T419
Test name
Test status
Simulation time 1780151285 ps
CPU time 24.87 seconds
Started Jun 09 01:34:13 PM PDT 24
Finished Jun 09 01:34:38 PM PDT 24
Peak memory 198016 kb
Host smart-cc71c3d0-ac67-4fa0-b48c-417fca2db3d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434358015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3434358015
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.4049784532
Short name T643
Test name
Test status
Simulation time 222637707 ps
CPU time 1 seconds
Started Jun 09 01:34:16 PM PDT 24
Finished Jun 09 01:34:17 PM PDT 24
Peak memory 198040 kb
Host smart-1d0d1fc3-e758-4a1c-bc23-48d74583d8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049784532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.4049784532
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.676740199
Short name T212
Test name
Test status
Simulation time 191758362 ps
CPU time 1.26 seconds
Started Jun 09 01:34:11 PM PDT 24
Finished Jun 09 01:34:13 PM PDT 24
Peak memory 197064 kb
Host smart-4a9f9d00-b9e1-4361-89a9-e4fbdea5a9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676740199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.676740199
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2713027937
Short name T245
Test name
Test status
Simulation time 182586637 ps
CPU time 1.88 seconds
Started Jun 09 01:34:12 PM PDT 24
Finished Jun 09 01:34:14 PM PDT 24
Peak memory 198136 kb
Host smart-cf3a371e-848e-43fd-bd4c-14bf08911734
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713027937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2713027937
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.201044618
Short name T109
Test name
Test status
Simulation time 357463730 ps
CPU time 2.02 seconds
Started Jun 09 01:34:11 PM PDT 24
Finished Jun 09 01:34:14 PM PDT 24
Peak memory 196896 kb
Host smart-6c27a38c-89cd-4a72-86c6-3b34047d0022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201044618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.201044618
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3124758313
Short name T182
Test name
Test status
Simulation time 14590801 ps
CPU time 0.66 seconds
Started Jun 09 01:34:13 PM PDT 24
Finished Jun 09 01:34:14 PM PDT 24
Peak memory 194368 kb
Host smart-dbe406ac-f378-47d6-8d12-f702c038e5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124758313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3124758313
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.343855342
Short name T565
Test name
Test status
Simulation time 103464895 ps
CPU time 1.35 seconds
Started Jun 09 01:34:12 PM PDT 24
Finished Jun 09 01:34:13 PM PDT 24
Peak memory 198076 kb
Host smart-84cef175-cbae-4ad8-a539-209a0b4ff535
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343855342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.343855342
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2662170436
Short name T603
Test name
Test status
Simulation time 641766687 ps
CPU time 5.53 seconds
Started Jun 09 01:34:24 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 198024 kb
Host smart-d90c886d-41d8-4a5f-b9a7-b66f00c72436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662170436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2662170436
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.335860242
Short name T38
Test name
Test status
Simulation time 361395324 ps
CPU time 0.91 seconds
Started Jun 09 01:34:19 PM PDT 24
Finished Jun 09 01:34:20 PM PDT 24
Peak memory 215008 kb
Host smart-49a60862-8036-4258-a33f-53e9ea9c7705
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335860242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.335860242
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2405872779
Short name T379
Test name
Test status
Simulation time 153543580 ps
CPU time 1.4 seconds
Started Jun 09 01:34:11 PM PDT 24
Finished Jun 09 01:34:13 PM PDT 24
Peak memory 196224 kb
Host smart-c475fc25-b86a-49a3-b8e5-881ce8355c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405872779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2405872779
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2491502448
Short name T64
Test name
Test status
Simulation time 105869084 ps
CPU time 1.03 seconds
Started Jun 09 01:34:12 PM PDT 24
Finished Jun 09 01:34:13 PM PDT 24
Peak memory 195932 kb
Host smart-7c3a8b09-7cfe-454c-97d1-18a38b9fb6bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491502448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2491502448
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4161724965
Short name T634
Test name
Test status
Simulation time 25751878134 ps
CPU time 167.31 seconds
Started Jun 09 01:34:16 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 198208 kb
Host smart-7c335403-1c3b-4b50-8aae-b800d82b8390
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161724965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4161724965
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.260012284
Short name T59
Test name
Test status
Simulation time 69525255856 ps
CPU time 940.71 seconds
Started Jun 09 01:34:17 PM PDT 24
Finished Jun 09 01:49:58 PM PDT 24
Peak memory 198268 kb
Host smart-09b02f94-b442-44d5-a248-1d29a3c1982a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=260012284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.260012284
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3234644629
Short name T327
Test name
Test status
Simulation time 49006464 ps
CPU time 0.59 seconds
Started Jun 09 01:34:56 PM PDT 24
Finished Jun 09 01:34:56 PM PDT 24
Peak memory 195672 kb
Host smart-10df8153-a012-4ffe-8732-c60b5cd22ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234644629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3234644629
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1102752419
Short name T142
Test name
Test status
Simulation time 118822003 ps
CPU time 0.83 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:55 PM PDT 24
Peak memory 195312 kb
Host smart-bcd40303-32f8-4511-92c2-b6522bdcb127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102752419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1102752419
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3458843729
Short name T457
Test name
Test status
Simulation time 249655173 ps
CPU time 13.15 seconds
Started Jun 09 01:34:50 PM PDT 24
Finished Jun 09 01:35:04 PM PDT 24
Peak memory 198048 kb
Host smart-72065914-878c-468a-ba31-36553536f6d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458843729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3458843729
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3761474170
Short name T111
Test name
Test status
Simulation time 114706923 ps
CPU time 0.91 seconds
Started Jun 09 01:34:53 PM PDT 24
Finished Jun 09 01:34:54 PM PDT 24
Peak memory 195972 kb
Host smart-6053e6e0-3ccb-4cb2-8a97-7623dd9421f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761474170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3761474170
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3267935193
Short name T371
Test name
Test status
Simulation time 31099969 ps
CPU time 0.68 seconds
Started Jun 09 01:34:53 PM PDT 24
Finished Jun 09 01:34:54 PM PDT 24
Peak memory 194436 kb
Host smart-f3f40914-96ba-4eb1-8a98-47334247d35f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267935193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3267935193
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.427813422
Short name T386
Test name
Test status
Simulation time 211973356 ps
CPU time 2.06 seconds
Started Jun 09 01:34:50 PM PDT 24
Finished Jun 09 01:34:52 PM PDT 24
Peak memory 198060 kb
Host smart-9e8b650c-3d1b-41ff-a691-69d7d3b52a85
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427813422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.427813422
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1331868818
Short name T474
Test name
Test status
Simulation time 64615942 ps
CPU time 1.59 seconds
Started Jun 09 01:34:49 PM PDT 24
Finished Jun 09 01:34:51 PM PDT 24
Peak memory 196752 kb
Host smart-99e2c42b-eb3a-4654-86c1-c8ea95894c14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331868818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1331868818
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3824578953
Short name T170
Test name
Test status
Simulation time 50187121 ps
CPU time 1.13 seconds
Started Jun 09 01:34:48 PM PDT 24
Finished Jun 09 01:34:49 PM PDT 24
Peak memory 196096 kb
Host smart-714a4377-665a-4e98-9a56-2b2db9050f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824578953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3824578953
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.176274913
Short name T409
Test name
Test status
Simulation time 35578347 ps
CPU time 0.82 seconds
Started Jun 09 01:34:48 PM PDT 24
Finished Jun 09 01:34:49 PM PDT 24
Peak memory 197372 kb
Host smart-3f1eb7d7-8390-4da2-bbb3-bb8a31ecdbe8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176274913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.176274913
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.395093462
Short name T544
Test name
Test status
Simulation time 289085829 ps
CPU time 3.57 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:58 PM PDT 24
Peak memory 198036 kb
Host smart-44cddf3c-a53a-4042-8c7a-66509434f5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395093462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.395093462
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1236683
Short name T240
Test name
Test status
Simulation time 72198665 ps
CPU time 1.26 seconds
Started Jun 09 01:34:51 PM PDT 24
Finished Jun 09 01:34:52 PM PDT 24
Peak memory 195820 kb
Host smart-60d81fdc-e072-4b1f-94cd-0a4a5036e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1236683
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2568780050
Short name T452
Test name
Test status
Simulation time 44313040 ps
CPU time 0.95 seconds
Started Jun 09 01:34:50 PM PDT 24
Finished Jun 09 01:34:51 PM PDT 24
Peak memory 196576 kb
Host smart-06386b45-ef94-4760-bcc1-3b944805eab8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568780050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2568780050
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1026620872
Short name T675
Test name
Test status
Simulation time 160105907217 ps
CPU time 186.4 seconds
Started Jun 09 01:34:51 PM PDT 24
Finished Jun 09 01:37:58 PM PDT 24
Peak memory 198244 kb
Host smart-bd305e89-fc40-4d7e-9fcb-434951978347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026620872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1026620872
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1229379323
Short name T574
Test name
Test status
Simulation time 71011620596 ps
CPU time 473.68 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:42:48 PM PDT 24
Peak memory 198208 kb
Host smart-e72114a8-2eb4-4a5d-a469-ab3224da2c4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1229379323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1229379323
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.285328036
Short name T19
Test name
Test status
Simulation time 21853164 ps
CPU time 0.63 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:35:01 PM PDT 24
Peak memory 193960 kb
Host smart-c30e5d4e-dc45-44a0-8ec2-7dba99141fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285328036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.285328036
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1197492124
Short name T659
Test name
Test status
Simulation time 25232062 ps
CPU time 0.76 seconds
Started Jun 09 01:34:55 PM PDT 24
Finished Jun 09 01:34:56 PM PDT 24
Peak memory 195368 kb
Host smart-7b1f1f9d-6575-46e6-974e-84e30efb7978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197492124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1197492124
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1273721872
Short name T540
Test name
Test status
Simulation time 1855015829 ps
CPU time 13.08 seconds
Started Jun 09 01:34:53 PM PDT 24
Finished Jun 09 01:35:06 PM PDT 24
Peak memory 196252 kb
Host smart-30f1e5ca-dbbb-40cd-9243-d76e74554706
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273721872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1273721872
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1639384977
Short name T471
Test name
Test status
Simulation time 85300356 ps
CPU time 0.81 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:55 PM PDT 24
Peak memory 195972 kb
Host smart-062e4321-394f-4d5d-82ac-b48af7812d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639384977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1639384977
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3180234806
Short name T511
Test name
Test status
Simulation time 300905737 ps
CPU time 1.27 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:55 PM PDT 24
Peak memory 196692 kb
Host smart-f29d18eb-63c5-40e3-b657-06e779dd707b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180234806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3180234806
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.485045250
Short name T592
Test name
Test status
Simulation time 291485669 ps
CPU time 3.06 seconds
Started Jun 09 01:34:55 PM PDT 24
Finished Jun 09 01:34:58 PM PDT 24
Peak memory 198024 kb
Host smart-3267cf5b-8180-489d-8889-0830b96652fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485045250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.485045250
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.713719789
Short name T369
Test name
Test status
Simulation time 567413349 ps
CPU time 2.89 seconds
Started Jun 09 01:34:55 PM PDT 24
Finished Jun 09 01:34:58 PM PDT 24
Peak memory 195868 kb
Host smart-3f14d7a9-5e02-4c59-aff0-105ac52d5ead
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713719789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
713719789
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1438338312
Short name T557
Test name
Test status
Simulation time 81361692 ps
CPU time 0.95 seconds
Started Jun 09 01:34:56 PM PDT 24
Finished Jun 09 01:34:57 PM PDT 24
Peak memory 196052 kb
Host smart-f87e62ee-1c36-44de-8cb5-6b20bcba0b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438338312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1438338312
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.315956430
Short name T253
Test name
Test status
Simulation time 59473130 ps
CPU time 0.84 seconds
Started Jun 09 01:34:53 PM PDT 24
Finished Jun 09 01:34:54 PM PDT 24
Peak memory 196672 kb
Host smart-cb8e3b6e-fd56-4bf4-9380-c8a38c8e5a42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315956430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.315956430
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1835480357
Short name T5
Test name
Test status
Simulation time 558555193 ps
CPU time 6.86 seconds
Started Jun 09 01:34:55 PM PDT 24
Finished Jun 09 01:35:02 PM PDT 24
Peak memory 197996 kb
Host smart-dad2b5e9-cb08-4a7d-8cfa-f58bbcacfbe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835480357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1835480357
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.4144652271
Short name T583
Test name
Test status
Simulation time 45365861 ps
CPU time 0.95 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:55 PM PDT 24
Peak memory 195812 kb
Host smart-4cc9ecd4-4e87-4cfb-9cec-6ba5d30a8be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144652271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.4144652271
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.532433812
Short name T281
Test name
Test status
Simulation time 577258961 ps
CPU time 1.38 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:56 PM PDT 24
Peak memory 196476 kb
Host smart-bf7288d3-daae-417c-b294-716df14f6011
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532433812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.532433812
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1350220915
Short name T542
Test name
Test status
Simulation time 5821206889 ps
CPU time 81.23 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:36:22 PM PDT 24
Peak memory 198188 kb
Host smart-d676fdb7-b023-4343-aed3-fae12d63534a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350220915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1350220915
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.556604461
Short name T377
Test name
Test status
Simulation time 30552235 ps
CPU time 0.57 seconds
Started Jun 09 01:34:58 PM PDT 24
Finished Jun 09 01:34:59 PM PDT 24
Peak memory 194164 kb
Host smart-a96f5b29-6a1d-49c7-81de-84706087147a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556604461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.556604461
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2863335216
Short name T613
Test name
Test status
Simulation time 21072960 ps
CPU time 0.75 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:35:01 PM PDT 24
Peak memory 195376 kb
Host smart-6993bb76-6272-4ec8-b955-d04f80be0631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863335216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2863335216
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3870191602
Short name T696
Test name
Test status
Simulation time 345818372 ps
CPU time 18.07 seconds
Started Jun 09 01:34:59 PM PDT 24
Finished Jun 09 01:35:17 PM PDT 24
Peak memory 195568 kb
Host smart-325913e1-5261-4246-90d7-966e313c82fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870191602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3870191602
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.723871697
Short name T343
Test name
Test status
Simulation time 76807342 ps
CPU time 1.17 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:35:01 PM PDT 24
Peak memory 196580 kb
Host smart-ddef0552-fcc8-46b4-a338-ee103efa9633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723871697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.723871697
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2348783700
Short name T112
Test name
Test status
Simulation time 32900444 ps
CPU time 0.69 seconds
Started Jun 09 01:34:59 PM PDT 24
Finished Jun 09 01:35:00 PM PDT 24
Peak memory 195128 kb
Host smart-15ebdd90-25f5-43d4-9350-24f5d3624f30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348783700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2348783700
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3308052786
Short name T406
Test name
Test status
Simulation time 98670689 ps
CPU time 1.26 seconds
Started Jun 09 01:34:59 PM PDT 24
Finished Jun 09 01:35:00 PM PDT 24
Peak memory 198056 kb
Host smart-a7d17e0c-98fd-4ec1-91a1-1142e1e3cabc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308052786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3308052786
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.357124266
Short name T619
Test name
Test status
Simulation time 97040553 ps
CPU time 2.82 seconds
Started Jun 09 01:34:58 PM PDT 24
Finished Jun 09 01:35:01 PM PDT 24
Peak memory 197392 kb
Host smart-2c0df46e-956a-46f9-9f21-f922508a6451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357124266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
357124266
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.844266999
Short name T216
Test name
Test status
Simulation time 41468565 ps
CPU time 1.04 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:35:02 PM PDT 24
Peak memory 196132 kb
Host smart-51865d7e-8e0f-4979-9e1b-7056a79612c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844266999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.844266999
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.370353405
Short name T450
Test name
Test status
Simulation time 31209566 ps
CPU time 0.84 seconds
Started Jun 09 01:34:59 PM PDT 24
Finished Jun 09 01:35:00 PM PDT 24
Peak memory 195648 kb
Host smart-277125a7-b612-49ab-b71c-ba8766de9e99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370353405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.370353405
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_smoke.537125705
Short name T51
Test name
Test status
Simulation time 60028429 ps
CPU time 1.18 seconds
Started Jun 09 01:34:58 PM PDT 24
Finished Jun 09 01:35:00 PM PDT 24
Peak memory 196900 kb
Host smart-4dc70f4b-26ec-44bb-97e4-6235e8e38a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537125705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.537125705
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3296265845
Short name T305
Test name
Test status
Simulation time 67046134 ps
CPU time 0.94 seconds
Started Jun 09 01:34:59 PM PDT 24
Finished Jun 09 01:35:00 PM PDT 24
Peak memory 196552 kb
Host smart-24d24b5e-51d5-463d-9d1e-0aaa41b371cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296265845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3296265845
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1683588130
Short name T132
Test name
Test status
Simulation time 10219983339 ps
CPU time 146.43 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:37:26 PM PDT 24
Peak memory 198220 kb
Host smart-ae8f5ae9-9f85-4c2b-9bf5-4e3c90846859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683588130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1683588130
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.883264244
Short name T437
Test name
Test status
Simulation time 174620575590 ps
CPU time 3096.51 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 198248 kb
Host smart-cc80d65d-8371-4b31-8d0b-873a64856067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=883264244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.883264244
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.183617101
Short name T133
Test name
Test status
Simulation time 31791416 ps
CPU time 0.6 seconds
Started Jun 09 01:35:02 PM PDT 24
Finished Jun 09 01:35:02 PM PDT 24
Peak memory 194136 kb
Host smart-12d76ca1-859e-4adf-9f6d-9ef3c821457d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183617101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.183617101
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3186192872
Short name T167
Test name
Test status
Simulation time 20476699 ps
CPU time 0.67 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:35:05 PM PDT 24
Peak memory 194152 kb
Host smart-422c0ede-6eff-48b1-912d-2118b4cc9e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186192872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3186192872
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1306813042
Short name T573
Test name
Test status
Simulation time 1245319782 ps
CPU time 22.26 seconds
Started Jun 09 01:35:06 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 196260 kb
Host smart-95bbaea5-9404-4783-bc31-3c825ff63c69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306813042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1306813042
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2322201716
Short name T646
Test name
Test status
Simulation time 186322353 ps
CPU time 1.09 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:35:05 PM PDT 24
Peak memory 196712 kb
Host smart-49e4dc11-6e11-40b8-a8ff-a16f8c2039a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322201716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2322201716
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.417087387
Short name T95
Test name
Test status
Simulation time 93106166 ps
CPU time 1.24 seconds
Started Jun 09 01:35:06 PM PDT 24
Finished Jun 09 01:35:07 PM PDT 24
Peak memory 196184 kb
Host smart-081abb42-ea35-4dd1-9229-15ca372f44c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417087387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.417087387
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3251222013
Short name T328
Test name
Test status
Simulation time 96342914 ps
CPU time 3.93 seconds
Started Jun 09 01:35:04 PM PDT 24
Finished Jun 09 01:35:08 PM PDT 24
Peak memory 198128 kb
Host smart-d5a76ee4-670d-43ca-95e3-2b17ffe0b57d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251222013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3251222013
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2226645459
Short name T373
Test name
Test status
Simulation time 150420340 ps
CPU time 2.38 seconds
Started Jun 09 01:35:06 PM PDT 24
Finished Jun 09 01:35:08 PM PDT 24
Peak memory 198072 kb
Host smart-f7864144-03e5-4cd7-8767-25b72cf4c115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226645459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2226645459
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.4224864306
Short name T498
Test name
Test status
Simulation time 182168312 ps
CPU time 1.04 seconds
Started Jun 09 01:35:04 PM PDT 24
Finished Jun 09 01:35:05 PM PDT 24
Peak memory 196000 kb
Host smart-7b64f5ad-88b8-4e77-84ef-a6d92f3cefa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224864306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.4224864306
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3617108840
Short name T15
Test name
Test status
Simulation time 385314605 ps
CPU time 1.36 seconds
Started Jun 09 01:35:02 PM PDT 24
Finished Jun 09 01:35:03 PM PDT 24
Peak memory 195900 kb
Host smart-db382544-bb54-4c87-880a-70e7c5c72e26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617108840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3617108840
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.544777335
Short name T641
Test name
Test status
Simulation time 109678956 ps
CPU time 2.67 seconds
Started Jun 09 01:35:06 PM PDT 24
Finished Jun 09 01:35:09 PM PDT 24
Peak memory 197984 kb
Host smart-6bd98d38-8a7e-4414-9733-47a1f07e0b2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544777335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.544777335
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1641525837
Short name T488
Test name
Test status
Simulation time 441211840 ps
CPU time 1.52 seconds
Started Jun 09 01:35:00 PM PDT 24
Finished Jun 09 01:35:02 PM PDT 24
Peak memory 197988 kb
Host smart-432ab8eb-554e-4405-964b-ea3d88d5d48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641525837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1641525837
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3496167903
Short name T708
Test name
Test status
Simulation time 89840144 ps
CPU time 0.99 seconds
Started Jun 09 01:34:58 PM PDT 24
Finished Jun 09 01:34:59 PM PDT 24
Peak memory 196588 kb
Host smart-f685a7ae-b375-48c5-808a-caca6a6a0305
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496167903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3496167903
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.398879480
Short name T266
Test name
Test status
Simulation time 16263066143 ps
CPU time 198.31 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:38:22 PM PDT 24
Peak memory 198188 kb
Host smart-0877c764-cd28-4ee3-af96-22125ed990be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398879480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.398879480
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1431270546
Short name T31
Test name
Test status
Simulation time 330302527058 ps
CPU time 1658.61 seconds
Started Jun 09 01:35:04 PM PDT 24
Finished Jun 09 02:02:44 PM PDT 24
Peak memory 198272 kb
Host smart-126e43b2-0ec2-473d-9001-679dd1ae836a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1431270546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1431270546
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3285788111
Short name T580
Test name
Test status
Simulation time 13089811 ps
CPU time 0.54 seconds
Started Jun 09 01:35:13 PM PDT 24
Finished Jun 09 01:35:14 PM PDT 24
Peak memory 194672 kb
Host smart-1e67a89f-4eeb-44fc-a1cb-bdf58a023b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285788111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3285788111
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.876703074
Short name T160
Test name
Test status
Simulation time 99281265 ps
CPU time 0.66 seconds
Started Jun 09 01:35:06 PM PDT 24
Finished Jun 09 01:35:07 PM PDT 24
Peak memory 194128 kb
Host smart-0d788018-c863-48b6-919d-08029cee90a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876703074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.876703074
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.594882123
Short name T217
Test name
Test status
Simulation time 302330659 ps
CPU time 3.6 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:35:07 PM PDT 24
Peak memory 195760 kb
Host smart-ded26100-6f42-46d5-8a61-18f3c64958b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594882123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.594882123
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2389950729
Short name T473
Test name
Test status
Simulation time 113724938 ps
CPU time 0.84 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:17 PM PDT 24
Peak memory 196348 kb
Host smart-6ef74cd2-a678-4724-b024-507c9d5d3515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389950729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2389950729
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3050050610
Short name T298
Test name
Test status
Simulation time 193831814 ps
CPU time 1 seconds
Started Jun 09 01:35:07 PM PDT 24
Finished Jun 09 01:35:08 PM PDT 24
Peak memory 195784 kb
Host smart-e5f425f5-aaa0-4595-a129-d06eb6f48cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050050610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3050050610
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.476965739
Short name T520
Test name
Test status
Simulation time 42616551 ps
CPU time 1.76 seconds
Started Jun 09 01:35:07 PM PDT 24
Finished Jun 09 01:35:09 PM PDT 24
Peak memory 197180 kb
Host smart-efcebd04-7954-46cb-ba1a-d81d8a20259f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476965739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.476965739
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4215562803
Short name T545
Test name
Test status
Simulation time 28689175 ps
CPU time 0.89 seconds
Started Jun 09 01:35:06 PM PDT 24
Finished Jun 09 01:35:07 PM PDT 24
Peak memory 195584 kb
Host smart-8f5a684c-568f-428a-b1e5-455693cf2fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215562803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4215562803
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.383295601
Short name T703
Test name
Test status
Simulation time 50693508 ps
CPU time 0.66 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:35:04 PM PDT 24
Peak memory 194392 kb
Host smart-a32e2e0c-aa0a-4779-8465-4351dcf55de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383295601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.383295601
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1541115860
Short name T250
Test name
Test status
Simulation time 94884112 ps
CPU time 1.1 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:35:05 PM PDT 24
Peak memory 196840 kb
Host smart-3c6d45a2-e002-4280-bdd4-a84dd5b6a6bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541115860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1541115860
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2446407099
Short name T188
Test name
Test status
Simulation time 362598406 ps
CPU time 5.8 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:23 PM PDT 24
Peak memory 198080 kb
Host smart-f99a81af-8571-4b4c-a7d6-dae1ec4ad56b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446407099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2446407099
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1095590425
Short name T118
Test name
Test status
Simulation time 56326205 ps
CPU time 0.89 seconds
Started Jun 09 01:35:03 PM PDT 24
Finished Jun 09 01:35:04 PM PDT 24
Peak memory 195536 kb
Host smart-23f4469f-9835-40a8-8f28-49c045b98ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095590425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1095590425
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3118318434
Short name T331
Test name
Test status
Simulation time 142687186 ps
CPU time 1.19 seconds
Started Jun 09 01:35:05 PM PDT 24
Finished Jun 09 01:35:06 PM PDT 24
Peak memory 196580 kb
Host smart-a3e04ee5-0595-48f2-83de-b61c617574cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118318434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3118318434
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.418037541
Short name T414
Test name
Test status
Simulation time 6279832639 ps
CPU time 84.11 seconds
Started Jun 09 01:35:14 PM PDT 24
Finished Jun 09 01:36:38 PM PDT 24
Peak memory 198232 kb
Host smart-673c4887-8686-46c0-8ab2-0057c03bc6ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418037541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.418037541
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3392010503
Short name T326
Test name
Test status
Simulation time 17484018 ps
CPU time 0.6 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:17 PM PDT 24
Peak memory 194648 kb
Host smart-f9d9677f-eee5-4c20-9aba-77063581aff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392010503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3392010503
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3040138125
Short name T145
Test name
Test status
Simulation time 89248596 ps
CPU time 0.72 seconds
Started Jun 09 01:35:15 PM PDT 24
Finished Jun 09 01:35:15 PM PDT 24
Peak memory 195240 kb
Host smart-2ccbf81d-c617-4da4-bb6e-f3f3ce5f5bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040138125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3040138125
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2959884843
Short name T660
Test name
Test status
Simulation time 1710204616 ps
CPU time 12.02 seconds
Started Jun 09 01:35:15 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 196848 kb
Host smart-d2d3ba17-e3d6-482f-9a9c-0abeaadb50d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959884843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2959884843
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.139580010
Short name T285
Test name
Test status
Simulation time 423868079 ps
CPU time 0.66 seconds
Started Jun 09 01:35:13 PM PDT 24
Finished Jun 09 01:35:13 PM PDT 24
Peak memory 195312 kb
Host smart-87fc5046-c9a0-4158-9f66-7fe92c2e8bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139580010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.139580010
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.321446886
Short name T433
Test name
Test status
Simulation time 204068492 ps
CPU time 1.4 seconds
Started Jun 09 01:35:15 PM PDT 24
Finished Jun 09 01:35:17 PM PDT 24
Peak memory 198088 kb
Host smart-9323deb4-9a95-470d-96a0-b7a76a51a95c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321446886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.321446886
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1511123085
Short name T105
Test name
Test status
Simulation time 27624049 ps
CPU time 1.12 seconds
Started Jun 09 01:35:14 PM PDT 24
Finished Jun 09 01:35:16 PM PDT 24
Peak memory 197480 kb
Host smart-f9bc1591-d357-4094-8ca4-4b9c4cb34ae7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511123085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1511123085
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1018144031
Short name T397
Test name
Test status
Simulation time 117585809 ps
CPU time 2.35 seconds
Started Jun 09 01:35:14 PM PDT 24
Finished Jun 09 01:35:16 PM PDT 24
Peak memory 197180 kb
Host smart-1215839e-7ac4-4883-831b-83c5309e3c71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018144031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1018144031
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3544047834
Short name T49
Test name
Test status
Simulation time 23243100 ps
CPU time 0.87 seconds
Started Jun 09 01:35:13 PM PDT 24
Finished Jun 09 01:35:15 PM PDT 24
Peak memory 197396 kb
Host smart-e9dde5c2-e122-44db-acb8-73d72b7ccd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544047834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3544047834
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3375861178
Short name T349
Test name
Test status
Simulation time 23676527 ps
CPU time 0.76 seconds
Started Jun 09 01:35:13 PM PDT 24
Finished Jun 09 01:35:14 PM PDT 24
Peak memory 195524 kb
Host smart-03d3c590-b825-4d05-9857-672b8736af46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375861178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3375861178
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3976953576
Short name T644
Test name
Test status
Simulation time 259464158 ps
CPU time 6.06 seconds
Started Jun 09 01:35:14 PM PDT 24
Finished Jun 09 01:35:21 PM PDT 24
Peak memory 198088 kb
Host smart-a58bd3f5-83d3-4a4f-b4d4-a91d91dff847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976953576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3976953576
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3619903526
Short name T408
Test name
Test status
Simulation time 601296083 ps
CPU time 1.11 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:17 PM PDT 24
Peak memory 195788 kb
Host smart-5570b0ef-9a30-4a80-9a73-6ecf9cf0b8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619903526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3619903526
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1354011938
Short name T235
Test name
Test status
Simulation time 44295169 ps
CPU time 0.91 seconds
Started Jun 09 01:35:13 PM PDT 24
Finished Jun 09 01:35:14 PM PDT 24
Peak memory 196008 kb
Host smart-47e98647-f9b7-4bff-a4e4-26e5885870d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354011938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1354011938
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1981249283
Short name T9
Test name
Test status
Simulation time 14927072624 ps
CPU time 81.59 seconds
Started Jun 09 01:35:12 PM PDT 24
Finished Jun 09 01:36:34 PM PDT 24
Peak memory 198244 kb
Host smart-15903389-adf1-44da-86b3-573d4d537b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981249283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1981249283
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.344257752
Short name T467
Test name
Test status
Simulation time 27442290209 ps
CPU time 457.42 seconds
Started Jun 09 01:35:12 PM PDT 24
Finished Jun 09 01:42:49 PM PDT 24
Peak memory 198268 kb
Host smart-b78a8cd4-c6ca-4f81-b34b-8661bdfe8d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=344257752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.344257752
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3942515595
Short name T658
Test name
Test status
Simulation time 39719334 ps
CPU time 0.59 seconds
Started Jun 09 01:35:23 PM PDT 24
Finished Jun 09 01:35:24 PM PDT 24
Peak memory 193948 kb
Host smart-df5406ad-733f-44e3-89ab-64433dbe6aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942515595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3942515595
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2677058935
Short name T623
Test name
Test status
Simulation time 52249412 ps
CPU time 0.91 seconds
Started Jun 09 01:35:17 PM PDT 24
Finished Jun 09 01:35:18 PM PDT 24
Peak memory 195956 kb
Host smart-f2993ad0-dc35-470c-8d9b-0ed914cd7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677058935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2677058935
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.165394231
Short name T553
Test name
Test status
Simulation time 421710178 ps
CPU time 12.89 seconds
Started Jun 09 01:35:19 PM PDT 24
Finished Jun 09 01:35:32 PM PDT 24
Peak memory 196912 kb
Host smart-cca17958-26dd-497a-8070-52cb43ceecf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165394231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.165394231
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1369228701
Short name T3
Test name
Test status
Simulation time 44031386 ps
CPU time 0.75 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:25 PM PDT 24
Peak memory 195948 kb
Host smart-a2afc4a4-a6d6-4d2a-bb7f-278426b008bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369228701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1369228701
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1928193667
Short name T165
Test name
Test status
Simulation time 80578205 ps
CPU time 1.22 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:18 PM PDT 24
Peak memory 196108 kb
Host smart-93d34ffd-2a88-4071-a75b-0f89d15929df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928193667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1928193667
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3889493118
Short name T510
Test name
Test status
Simulation time 128026739 ps
CPU time 2.59 seconds
Started Jun 09 01:35:17 PM PDT 24
Finished Jun 09 01:35:20 PM PDT 24
Peak memory 198156 kb
Host smart-acc26750-68e0-431f-a3a2-dd45802502e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889493118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3889493118
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2142725952
Short name T591
Test name
Test status
Simulation time 392226897 ps
CPU time 1.47 seconds
Started Jun 09 01:35:19 PM PDT 24
Finished Jun 09 01:35:21 PM PDT 24
Peak memory 196176 kb
Host smart-93ecc257-5d11-42e2-9223-2da202e6b48e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142725952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2142725952
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3886415770
Short name T335
Test name
Test status
Simulation time 114162135 ps
CPU time 0.84 seconds
Started Jun 09 01:35:17 PM PDT 24
Finished Jun 09 01:35:18 PM PDT 24
Peak memory 196736 kb
Host smart-9236a97d-b521-4250-9443-c7acc4ae548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886415770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3886415770
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3503434345
Short name T569
Test name
Test status
Simulation time 34761524 ps
CPU time 1.29 seconds
Started Jun 09 01:35:17 PM PDT 24
Finished Jun 09 01:35:18 PM PDT 24
Peak memory 197080 kb
Host smart-b047e574-8d70-4f2e-ab91-cfe7df83e3ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503434345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3503434345
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2768409200
Short name T129
Test name
Test status
Simulation time 2094446675 ps
CPU time 6.47 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:22 PM PDT 24
Peak memory 198008 kb
Host smart-ad6bfe2a-097d-4550-be9d-42972ee87262
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768409200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2768409200
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3958681254
Short name T230
Test name
Test status
Simulation time 111449261 ps
CPU time 1.28 seconds
Started Jun 09 01:35:13 PM PDT 24
Finished Jun 09 01:35:15 PM PDT 24
Peak memory 195940 kb
Host smart-cb60f823-5b9d-4ec3-bf41-2d76904c3703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958681254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3958681254
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.245369875
Short name T490
Test name
Test status
Simulation time 58292476 ps
CPU time 1.13 seconds
Started Jun 09 01:35:16 PM PDT 24
Finished Jun 09 01:35:17 PM PDT 24
Peak memory 195608 kb
Host smart-b6d123df-cefa-473f-8b89-94d8d3de6888
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245369875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.245369875
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2491892854
Short name T453
Test name
Test status
Simulation time 17383108710 ps
CPU time 143.93 seconds
Started Jun 09 01:35:23 PM PDT 24
Finished Jun 09 01:37:48 PM PDT 24
Peak memory 198276 kb
Host smart-7c9d853e-b3a9-4eb4-a582-8aed414ca55d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491892854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2491892854
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3730994014
Short name T713
Test name
Test status
Simulation time 149037652135 ps
CPU time 538.19 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:44:24 PM PDT 24
Peak memory 198276 kb
Host smart-f88fa344-0619-48e4-82cd-fb9ae3143d3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3730994014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3730994014
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.961473505
Short name T46
Test name
Test status
Simulation time 63779617 ps
CPU time 0.6 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:35:26 PM PDT 24
Peak memory 193924 kb
Host smart-64453a75-1a22-45db-83db-3e3deed0ee1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961473505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.961473505
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2454240674
Short name T52
Test name
Test status
Simulation time 25530677 ps
CPU time 0.8 seconds
Started Jun 09 01:35:23 PM PDT 24
Finished Jun 09 01:35:24 PM PDT 24
Peak memory 195364 kb
Host smart-244c5ace-8434-4254-a0cf-b0af3e22f581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454240674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2454240674
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1858186024
Short name T256
Test name
Test status
Simulation time 825966216 ps
CPU time 28.95 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:35:54 PM PDT 24
Peak memory 196848 kb
Host smart-81f69024-9227-430e-a51d-ef798b202848
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858186024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1858186024
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2161950640
Short name T201
Test name
Test status
Simulation time 315713358 ps
CPU time 0.92 seconds
Started Jun 09 01:35:22 PM PDT 24
Finished Jun 09 01:35:24 PM PDT 24
Peak memory 197380 kb
Host smart-00311f78-5971-4e1f-9f68-3f74427007d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161950640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2161950640
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3568004161
Short name T546
Test name
Test status
Simulation time 64170922 ps
CPU time 1 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:25 PM PDT 24
Peak memory 196044 kb
Host smart-468a1176-621e-4705-b305-a2b358838418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568004161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3568004161
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1607664552
Short name T244
Test name
Test status
Simulation time 73321244 ps
CPU time 2.91 seconds
Started Jun 09 01:35:23 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 198036 kb
Host smart-1a888bca-36c9-4d4c-ae06-f2f96f9dbe03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607664552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1607664552
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.762994529
Short name T241
Test name
Test status
Simulation time 169811997 ps
CPU time 3.04 seconds
Started Jun 09 01:35:23 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 197240 kb
Host smart-55cf89cf-f549-42fe-8c42-d0123677aa92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762994529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
762994529
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3170569014
Short name T572
Test name
Test status
Simulation time 19858231 ps
CPU time 0.68 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:25 PM PDT 24
Peak memory 194320 kb
Host smart-04ac9344-1ff8-43e3-a91f-546c7c6f739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170569014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3170569014
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4113282325
Short name T208
Test name
Test status
Simulation time 168620884 ps
CPU time 1.29 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:35:26 PM PDT 24
Peak memory 196996 kb
Host smart-81a48135-95fa-480a-b841-7cb74a8466dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113282325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4113282325
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3654870299
Short name T489
Test name
Test status
Simulation time 471767683 ps
CPU time 5.47 seconds
Started Jun 09 01:35:27 PM PDT 24
Finished Jun 09 01:35:33 PM PDT 24
Peak memory 198096 kb
Host smart-feb5539f-36c2-4552-8308-532eefff7ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654870299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3654870299
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2861576403
Short name T444
Test name
Test status
Simulation time 39170603 ps
CPU time 1.21 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 198068 kb
Host smart-e02d7ebb-d7aa-4f8c-a0fe-40ba1394a30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861576403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2861576403
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.947631922
Short name T66
Test name
Test status
Simulation time 323436653 ps
CPU time 1.21 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 195568 kb
Host smart-c6b93cc0-a355-45bf-a444-1c2ff95cbca1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947631922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.947631922
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2710723060
Short name T130
Test name
Test status
Simulation time 11297973012 ps
CPU time 146.89 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:37:53 PM PDT 24
Peak memory 198256 kb
Host smart-286f96c4-2993-4edf-bd36-6e713c7494a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710723060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2710723060
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3052168135
Short name T63
Test name
Test status
Simulation time 26319970 ps
CPU time 0.59 seconds
Started Jun 09 01:35:34 PM PDT 24
Finished Jun 09 01:35:35 PM PDT 24
Peak memory 194660 kb
Host smart-c3b211a9-2ab4-41e7-86df-bad3305044c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052168135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3052168135
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.447599994
Short name T293
Test name
Test status
Simulation time 161261537 ps
CPU time 0.86 seconds
Started Jun 09 01:35:22 PM PDT 24
Finished Jun 09 01:35:23 PM PDT 24
Peak memory 196416 kb
Host smart-00aac22d-4e0c-43d6-ae6e-c64d7340b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447599994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.447599994
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1394924455
Short name T272
Test name
Test status
Simulation time 1757528264 ps
CPU time 12.35 seconds
Started Jun 09 01:35:30 PM PDT 24
Finished Jun 09 01:35:43 PM PDT 24
Peak memory 195504 kb
Host smart-266f80a6-8e7d-4875-9825-286b36902cb8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394924455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1394924455
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2957933402
Short name T221
Test name
Test status
Simulation time 86943647 ps
CPU time 0.67 seconds
Started Jun 09 01:35:27 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 194904 kb
Host smart-d0da529c-22e2-438a-aeb3-2acae90dd5c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957933402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2957933402
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2516961248
Short name T108
Test name
Test status
Simulation time 36928676 ps
CPU time 1.02 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:25 PM PDT 24
Peak memory 195956 kb
Host smart-ab721baf-2a93-4f1a-a770-34ef0c43e957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516961248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2516961248
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4038878882
Short name T14
Test name
Test status
Simulation time 62552127 ps
CPU time 1.95 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:26 PM PDT 24
Peak memory 196816 kb
Host smart-d68be3f4-cfa9-46e6-ac43-464b53670f3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038878882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4038878882
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3615021580
Short name T470
Test name
Test status
Simulation time 24433791 ps
CPU time 0.89 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:25 PM PDT 24
Peak memory 196480 kb
Host smart-6ede9926-f043-4750-a2cc-2f9fd914c33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615021580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3615021580
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.271018103
Short name T640
Test name
Test status
Simulation time 75640813 ps
CPU time 0.81 seconds
Started Jun 09 01:35:28 PM PDT 24
Finished Jun 09 01:35:29 PM PDT 24
Peak memory 195528 kb
Host smart-675f2c61-4ebe-4c51-8e92-9c65fa137ea5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271018103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.271018103
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1837764270
Short name T17
Test name
Test status
Simulation time 349036545 ps
CPU time 3.25 seconds
Started Jun 09 01:35:24 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 198052 kb
Host smart-2f718f19-3559-4685-863f-b5a1d8ccf3a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837764270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1837764270
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.613777931
Short name T448
Test name
Test status
Simulation time 77739221 ps
CPU time 1.36 seconds
Started Jun 09 01:35:23 PM PDT 24
Finished Jun 09 01:35:25 PM PDT 24
Peak memory 198068 kb
Host smart-816137c7-c078-4423-b01f-b6abe4c302f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613777931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.613777931
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3828085572
Short name T151
Test name
Test status
Simulation time 261544291 ps
CPU time 1.31 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 196348 kb
Host smart-2690eced-ba26-4ba3-94c2-e11828c02878
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828085572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3828085572
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3780447732
Short name T464
Test name
Test status
Simulation time 13795091430 ps
CPU time 102.66 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:37:21 PM PDT 24
Peak memory 198180 kb
Host smart-b206b409-d819-47f0-ae84-7de95f2975d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780447732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3780447732
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.223764013
Short name T32
Test name
Test status
Simulation time 33254665808 ps
CPU time 743.12 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:47:58 PM PDT 24
Peak memory 198272 kb
Host smart-83c9237b-54a9-4c02-9356-93a7058098bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=223764013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.223764013
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3501079247
Short name T199
Test name
Test status
Simulation time 12329771 ps
CPU time 0.53 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 193952 kb
Host smart-9d6ec781-1473-4fe6-bd2a-705c8da1c335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501079247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3501079247
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.501579449
Short name T456
Test name
Test status
Simulation time 17545366 ps
CPU time 0.69 seconds
Started Jun 09 01:35:30 PM PDT 24
Finished Jun 09 01:35:31 PM PDT 24
Peak memory 194932 kb
Host smart-d58770a5-e4a3-48a1-9738-89bfd89a38c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501579449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.501579449
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.304243351
Short name T247
Test name
Test status
Simulation time 648320256 ps
CPU time 21.46 seconds
Started Jun 09 01:35:32 PM PDT 24
Finished Jun 09 01:35:53 PM PDT 24
Peak memory 196696 kb
Host smart-8e3d67fb-fde6-4834-b099-b3092d46049e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304243351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.304243351
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.222975901
Short name T368
Test name
Test status
Simulation time 237195937 ps
CPU time 0.79 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 196060 kb
Host smart-cbca5019-ed54-4ee0-9001-bc82a345011b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222975901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.222975901
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1845461723
Short name T317
Test name
Test status
Simulation time 48728069 ps
CPU time 0.7 seconds
Started Jun 09 01:35:33 PM PDT 24
Finished Jun 09 01:35:34 PM PDT 24
Peak memory 194364 kb
Host smart-46da1644-2c34-444b-9481-cec5ecbdce55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845461723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1845461723
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2904181369
Short name T315
Test name
Test status
Simulation time 37907053 ps
CPU time 0.88 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 196248 kb
Host smart-7ccabf31-6fab-4c09-b4e5-986193eac400
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904181369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2904181369
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2005080139
Short name T449
Test name
Test status
Simulation time 128856889 ps
CPU time 1.46 seconds
Started Jun 09 01:35:27 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 196836 kb
Host smart-1e0dfd8d-2d62-4ce5-900c-788c0b0b5f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005080139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2005080139
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2402589222
Short name T193
Test name
Test status
Simulation time 30877054 ps
CPU time 1.07 seconds
Started Jun 09 01:35:32 PM PDT 24
Finished Jun 09 01:35:34 PM PDT 24
Peak memory 196696 kb
Host smart-dbe0547b-c0c3-4946-8941-5d136fa10116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402589222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2402589222
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3422002950
Short name T149
Test name
Test status
Simulation time 154501018 ps
CPU time 0.97 seconds
Started Jun 09 01:35:32 PM PDT 24
Finished Jun 09 01:35:34 PM PDT 24
Peak memory 196548 kb
Host smart-80cb511f-a7e2-419d-b251-543e200a82a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422002950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3422002950
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.748990233
Short name T254
Test name
Test status
Simulation time 218143761 ps
CPU time 3.64 seconds
Started Jun 09 01:35:25 PM PDT 24
Finished Jun 09 01:35:29 PM PDT 24
Peak memory 198024 kb
Host smart-35a8019b-c366-4173-a866-0567f046e1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748990233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.748990233
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2972852276
Short name T139
Test name
Test status
Simulation time 52601144 ps
CPU time 1.38 seconds
Started Jun 09 01:35:33 PM PDT 24
Finished Jun 09 01:35:34 PM PDT 24
Peak memory 196320 kb
Host smart-8664789d-881e-481e-abc5-8ec5b8208dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972852276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2972852276
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3933368159
Short name T116
Test name
Test status
Simulation time 44036814 ps
CPU time 1.1 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:27 PM PDT 24
Peak memory 195808 kb
Host smart-f96f80b2-76c8-49a0-bb46-cc5822b9db5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933368159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3933368159
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.128978069
Short name T205
Test name
Test status
Simulation time 6269681155 ps
CPU time 73.17 seconds
Started Jun 09 01:35:27 PM PDT 24
Finished Jun 09 01:36:40 PM PDT 24
Peak memory 198240 kb
Host smart-ae6cd379-ef56-4dbe-8113-fec7ca677687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128978069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.128978069
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.349314634
Short name T418
Test name
Test status
Simulation time 13822020 ps
CPU time 0.57 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:23 PM PDT 24
Peak memory 194080 kb
Host smart-aa0e6846-ce78-483d-afa6-35f9c2645ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349314634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.349314634
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2347306635
Short name T404
Test name
Test status
Simulation time 182343846 ps
CPU time 0.82 seconds
Started Jun 09 01:34:15 PM PDT 24
Finished Jun 09 01:34:16 PM PDT 24
Peak memory 195296 kb
Host smart-87c94321-9e8d-4c9f-9a9f-441f053b583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347306635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2347306635
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2972176244
Short name T582
Test name
Test status
Simulation time 1807393133 ps
CPU time 6.91 seconds
Started Jun 09 01:34:15 PM PDT 24
Finished Jun 09 01:34:23 PM PDT 24
Peak memory 196924 kb
Host smart-99fd0a34-fecd-47ec-8f8c-9f361ecde673
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972176244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2972176244
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.937750919
Short name T257
Test name
Test status
Simulation time 238056602 ps
CPU time 0.89 seconds
Started Jun 09 01:34:24 PM PDT 24
Finished Jun 09 01:34:25 PM PDT 24
Peak memory 197236 kb
Host smart-9bad0a8d-21de-4e89-880a-f8c54936eb1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937750919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.937750919
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1659233785
Short name T552
Test name
Test status
Simulation time 264378972 ps
CPU time 1.24 seconds
Started Jun 09 01:34:16 PM PDT 24
Finished Jun 09 01:34:18 PM PDT 24
Peak memory 196016 kb
Host smart-4fa192be-d358-45f4-a28c-de9fe7ad9b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659233785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1659233785
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3771544322
Short name T209
Test name
Test status
Simulation time 142917218 ps
CPU time 3.13 seconds
Started Jun 09 01:34:19 PM PDT 24
Finished Jun 09 01:34:22 PM PDT 24
Peak memory 198144 kb
Host smart-ff0101a4-aeb0-4b67-add6-33072257949f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771544322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3771544322
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2391424073
Short name T666
Test name
Test status
Simulation time 582435509 ps
CPU time 2.87 seconds
Started Jun 09 01:34:17 PM PDT 24
Finished Jun 09 01:34:20 PM PDT 24
Peak memory 198072 kb
Host smart-e85fd2f7-5af9-4214-b785-365427e51c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391424073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2391424073
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2941366273
Short name T223
Test name
Test status
Simulation time 60126661 ps
CPU time 1.35 seconds
Started Jun 09 01:34:17 PM PDT 24
Finished Jun 09 01:34:19 PM PDT 24
Peak memory 198092 kb
Host smart-c82fccda-59db-4303-abe6-b6314844dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941366273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2941366273
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.204452708
Short name T306
Test name
Test status
Simulation time 240060563 ps
CPU time 1.22 seconds
Started Jun 09 01:34:18 PM PDT 24
Finished Jun 09 01:34:19 PM PDT 24
Peak memory 197152 kb
Host smart-e58489bb-13b0-4b0f-bf1c-f4564fce5d1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204452708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.204452708
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3049912441
Short name T153
Test name
Test status
Simulation time 336518230 ps
CPU time 5.37 seconds
Started Jun 09 01:34:16 PM PDT 24
Finished Jun 09 01:34:22 PM PDT 24
Peak memory 198024 kb
Host smart-477896d8-a91b-4f87-b671-a9e120f73154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049912441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3049912441
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2488072216
Short name T36
Test name
Test status
Simulation time 398581876 ps
CPU time 1 seconds
Started Jun 09 01:34:26 PM PDT 24
Finished Jun 09 01:34:27 PM PDT 24
Peak memory 215012 kb
Host smart-d68f592f-ebed-467f-bb01-977b47a37504
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488072216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2488072216
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2562828840
Short name T360
Test name
Test status
Simulation time 119759839 ps
CPU time 1.28 seconds
Started Jun 09 01:34:18 PM PDT 24
Finished Jun 09 01:34:20 PM PDT 24
Peak memory 198088 kb
Host smart-ca077f70-4135-4148-b056-74c89c00c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562828840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2562828840
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2063085685
Short name T443
Test name
Test status
Simulation time 52541098 ps
CPU time 1.33 seconds
Started Jun 09 01:34:16 PM PDT 24
Finished Jun 09 01:34:17 PM PDT 24
Peak memory 198096 kb
Host smart-2fb475ed-3923-4a94-a595-492567de3aeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063085685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2063085685
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2243753607
Short name T518
Test name
Test status
Simulation time 7553537804 ps
CPU time 219.4 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:38:02 PM PDT 24
Peak memory 198272 kb
Host smart-71a73ff0-266e-4e95-a62b-06ccfa20461a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243753607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2243753607
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3836427544
Short name T16
Test name
Test status
Simulation time 11541786 ps
CPU time 0.55 seconds
Started Jun 09 01:35:33 PM PDT 24
Finished Jun 09 01:35:34 PM PDT 24
Peak memory 192824 kb
Host smart-b95e1454-5904-4154-a097-755bf28d44ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836427544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3836427544
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2955826338
Short name T237
Test name
Test status
Simulation time 72413619 ps
CPU time 0.9 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 195800 kb
Host smart-4903d0d6-1ba1-4e66-a532-c2b76ea787d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955826338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2955826338
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.566331113
Short name T436
Test name
Test status
Simulation time 801758648 ps
CPU time 20.64 seconds
Started Jun 09 01:35:33 PM PDT 24
Finished Jun 09 01:35:54 PM PDT 24
Peak memory 197008 kb
Host smart-8972c915-cce6-4656-84a1-91c471c70ad0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566331113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.566331113
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3412283774
Short name T7
Test name
Test status
Simulation time 228989015 ps
CPU time 0.87 seconds
Started Jun 09 01:35:34 PM PDT 24
Finished Jun 09 01:35:35 PM PDT 24
Peak memory 196932 kb
Host smart-0d32082f-1771-4d05-b7a7-42749a34af08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412283774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3412283774
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2367619349
Short name T555
Test name
Test status
Simulation time 70161675 ps
CPU time 1.06 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 195916 kb
Host smart-0614f5e9-2986-45a8-bdab-9107b1a2c15d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367619349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2367619349
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1463803555
Short name T637
Test name
Test status
Simulation time 72279006 ps
CPU time 2.78 seconds
Started Jun 09 01:35:32 PM PDT 24
Finished Jun 09 01:35:36 PM PDT 24
Peak memory 198080 kb
Host smart-cb27c8cf-e7f2-49a5-bfa3-a62fb0924aa4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463803555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1463803555
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1127310983
Short name T319
Test name
Test status
Simulation time 1120791595 ps
CPU time 3.58 seconds
Started Jun 09 01:35:33 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 197276 kb
Host smart-cf5ce22d-a6c3-4765-a90f-b000f3b59f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127310983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1127310983
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.402809089
Short name T226
Test name
Test status
Simulation time 170038440 ps
CPU time 1.02 seconds
Started Jun 09 01:35:26 PM PDT 24
Finished Jun 09 01:35:28 PM PDT 24
Peak memory 196796 kb
Host smart-270407e0-a10a-4da6-b0de-ffac7d20b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402809089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.402809089
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.475625044
Short name T154
Test name
Test status
Simulation time 25981951 ps
CPU time 0.71 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:36 PM PDT 24
Peak memory 195476 kb
Host smart-c33398fa-32d0-4052-a6e9-5d74aa2a3a8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475625044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.475625044
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3419246483
Short name T423
Test name
Test status
Simulation time 76069618 ps
CPU time 3.43 seconds
Started Jun 09 01:35:34 PM PDT 24
Finished Jun 09 01:35:38 PM PDT 24
Peak memory 198080 kb
Host smart-ecbe345c-1710-4a6f-a9a5-474ff8dcc39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419246483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3419246483
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3013809914
Short name T134
Test name
Test status
Simulation time 39014024 ps
CPU time 1.13 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 195900 kb
Host smart-4c43bc8b-5727-4bc3-bda8-8652cffd644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013809914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3013809914
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4167344709
Short name T351
Test name
Test status
Simulation time 60326556 ps
CPU time 1.17 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 196608 kb
Host smart-8fd2fe55-eb03-4fd2-bc4d-8fc2c3985c92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167344709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4167344709
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1139545364
Short name T420
Test name
Test status
Simulation time 6256893465 ps
CPU time 43.27 seconds
Started Jun 09 01:35:36 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 198180 kb
Host smart-0919c30a-ed21-4afc-af74-5aa29429498f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139545364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1139545364
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3192325972
Short name T617
Test name
Test status
Simulation time 170804013942 ps
CPU time 854.09 seconds
Started Jun 09 01:35:36 PM PDT 24
Finished Jun 09 01:49:50 PM PDT 24
Peak memory 198272 kb
Host smart-ea53fc8f-67f6-415b-8d4d-587ea262eb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3192325972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3192325972
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3288120317
Short name T680
Test name
Test status
Simulation time 31025754 ps
CPU time 0.56 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 193944 kb
Host smart-04f3aaa2-6686-41df-a7f1-5c4551d3828a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288120317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3288120317
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4232607952
Short name T621
Test name
Test status
Simulation time 87053776 ps
CPU time 0.82 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:36 PM PDT 24
Peak memory 195508 kb
Host smart-fd94eb29-82a0-4a79-8d4e-bbc6d723dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232607952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4232607952
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.481086121
Short name T578
Test name
Test status
Simulation time 3974042221 ps
CPU time 26.55 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:36:04 PM PDT 24
Peak memory 197068 kb
Host smart-ec301b14-b241-406f-9ab3-4ce87a386ca8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481086121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.481086121
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1735523232
Short name T530
Test name
Test status
Simulation time 131313080 ps
CPU time 0.68 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 194760 kb
Host smart-cf1a7225-38e5-4c80-89f0-2f6a3d5b056c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735523232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1735523232
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.688501798
Short name T695
Test name
Test status
Simulation time 163918369 ps
CPU time 1.07 seconds
Started Jun 09 01:35:34 PM PDT 24
Finished Jun 09 01:35:35 PM PDT 24
Peak memory 195792 kb
Host smart-8cc02f9a-50b1-4468-8cf6-31c9a9e335ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688501798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.688501798
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1891244170
Short name T258
Test name
Test status
Simulation time 91363512 ps
CPU time 3.5 seconds
Started Jun 09 01:35:33 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 198024 kb
Host smart-b673bd55-3fd5-4764-a205-a8e26819ceaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891244170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1891244170
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1700771744
Short name T681
Test name
Test status
Simulation time 53810604 ps
CPU time 1.59 seconds
Started Jun 09 01:35:34 PM PDT 24
Finished Jun 09 01:35:36 PM PDT 24
Peak memory 196040 kb
Host smart-e5df3f95-bf10-44a9-b108-5e35b26a9bf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700771744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1700771744
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3211035825
Short name T173
Test name
Test status
Simulation time 45049169 ps
CPU time 0.88 seconds
Started Jun 09 01:35:34 PM PDT 24
Finished Jun 09 01:35:35 PM PDT 24
Peak memory 196640 kb
Host smart-1a371eca-e7f9-438f-b51e-e86ad7631237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211035825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3211035825
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2145710266
Short name T337
Test name
Test status
Simulation time 109157731 ps
CPU time 1.32 seconds
Started Jun 09 01:35:32 PM PDT 24
Finished Jun 09 01:35:34 PM PDT 24
Peak memory 197004 kb
Host smart-d625950a-54b9-4944-be68-2d518a8b0b77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145710266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2145710266
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2289278646
Short name T204
Test name
Test status
Simulation time 447078266 ps
CPU time 5.83 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:42 PM PDT 24
Peak memory 197980 kb
Host smart-acf1a559-91ee-48ba-a399-4286e77bfc70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289278646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2289278646
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.555787316
Short name T157
Test name
Test status
Simulation time 82807368 ps
CPU time 1.34 seconds
Started Jun 09 01:35:36 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 195864 kb
Host smart-db712a63-9072-4173-b265-3bd812e0c8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555787316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.555787316
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2756887368
Short name T543
Test name
Test status
Simulation time 129513280 ps
CPU time 0.9 seconds
Started Jun 09 01:35:31 PM PDT 24
Finished Jun 09 01:35:32 PM PDT 24
Peak memory 196404 kb
Host smart-8dc01c8d-0ac9-4ebc-8e64-142206d036e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756887368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2756887368
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1604725628
Short name T417
Test name
Test status
Simulation time 69460664354 ps
CPU time 213.85 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:39:11 PM PDT 24
Peak memory 198216 kb
Host smart-d55666e3-df77-4b43-a64a-770c76311567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604725628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1604725628
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2690045052
Short name T706
Test name
Test status
Simulation time 392987041532 ps
CPU time 2022.69 seconds
Started Jun 09 01:35:36 PM PDT 24
Finished Jun 09 02:09:19 PM PDT 24
Peak memory 198260 kb
Host smart-7acfd895-d345-419d-998a-5faf580fff60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2690045052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2690045052
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.220241181
Short name T239
Test name
Test status
Simulation time 18238821 ps
CPU time 0.58 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 194168 kb
Host smart-ecbe7cf9-6e3a-4fe9-a4c4-1420850c1c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220241181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.220241181
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3808995487
Short name T164
Test name
Test status
Simulation time 51317130 ps
CPU time 0.85 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:35:38 PM PDT 24
Peak memory 197072 kb
Host smart-dd155228-beb8-40d3-9bd2-90c46592566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808995487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3808995487
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2249820766
Short name T684
Test name
Test status
Simulation time 6109462753 ps
CPU time 14.96 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:54 PM PDT 24
Peak memory 196984 kb
Host smart-bfd183b2-18c3-4349-999f-239187603cd7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249820766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2249820766
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.17177299
Short name T180
Test name
Test status
Simulation time 17926817 ps
CPU time 0.64 seconds
Started Jun 09 01:35:40 PM PDT 24
Finished Jun 09 01:35:41 PM PDT 24
Peak memory 194532 kb
Host smart-29ac6fc2-863e-49c7-883c-63f30e26bc76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.17177299
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.331224388
Short name T300
Test name
Test status
Simulation time 27315045 ps
CPU time 0.72 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 195184 kb
Host smart-427300f9-3623-4707-9234-d32cc4dc1304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331224388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.331224388
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.4087056983
Short name T357
Test name
Test status
Simulation time 63256855 ps
CPU time 2.48 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:35:40 PM PDT 24
Peak memory 196456 kb
Host smart-5de47b1b-ffe0-47ec-b6e5-581e340ad847
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087056983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.4087056983
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2094832927
Short name T575
Test name
Test status
Simulation time 328408793 ps
CPU time 2.08 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 196952 kb
Host smart-2a6a0b98-d07c-4479-bfdb-e821fad3407d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094832927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2094832927
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2147403105
Short name T412
Test name
Test status
Simulation time 61620227 ps
CPU time 1.17 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 198076 kb
Host smart-2013c647-7aca-4cc0-a9f5-56d52a520570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147403105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2147403105
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3530894036
Short name T398
Test name
Test status
Simulation time 129523652 ps
CPU time 0.86 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 195940 kb
Host smart-9bd443aa-d543-46bd-a839-064a9ab63ef2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530894036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3530894036
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3651985858
Short name T679
Test name
Test status
Simulation time 2178590828 ps
CPU time 6.27 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:42 PM PDT 24
Peak memory 198108 kb
Host smart-7194553c-c0c2-4242-8455-ef5fc2b9b839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651985858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3651985858
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2857103950
Short name T651
Test name
Test status
Simulation time 255683503 ps
CPU time 1.29 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 196856 kb
Host smart-c7d88828-fd1e-4ff7-9f20-bc9a157dc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857103950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2857103950
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2799749152
Short name T155
Test name
Test status
Simulation time 56541096 ps
CPU time 1.15 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:35:37 PM PDT 24
Peak memory 196544 kb
Host smart-a835a207-1c5c-420e-9226-30798686ae31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799749152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2799749152
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2995018944
Short name T277
Test name
Test status
Simulation time 15855760814 ps
CPU time 58.04 seconds
Started Jun 09 01:35:35 PM PDT 24
Finished Jun 09 01:36:34 PM PDT 24
Peak memory 198184 kb
Host smart-36315f3f-b195-4bf1-a5ea-391a12cfca6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995018944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2995018944
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1558907638
Short name T163
Test name
Test status
Simulation time 22885782 ps
CPU time 0.61 seconds
Started Jun 09 01:35:48 PM PDT 24
Finished Jun 09 01:35:48 PM PDT 24
Peak memory 193920 kb
Host smart-4a7b6d71-7321-403a-ac2b-559dadf97672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558907638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1558907638
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.4102001979
Short name T502
Test name
Test status
Simulation time 41228102 ps
CPU time 0.58 seconds
Started Jun 09 01:35:44 PM PDT 24
Finished Jun 09 01:35:45 PM PDT 24
Peak memory 194184 kb
Host smart-e31bda77-6bf0-4235-b0db-4cc0c5c21065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102001979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.4102001979
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3214503195
Short name T629
Test name
Test status
Simulation time 198583339 ps
CPU time 10.57 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:35:56 PM PDT 24
Peak memory 197140 kb
Host smart-db902e5e-1f79-4437-9a23-e340ad4ed94b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214503195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3214503195
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.4152235226
Short name T656
Test name
Test status
Simulation time 72340504 ps
CPU time 0.96 seconds
Started Jun 09 01:35:44 PM PDT 24
Finished Jun 09 01:35:45 PM PDT 24
Peak memory 197216 kb
Host smart-1b93133f-33d5-4291-a00c-2c0c7690369b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152235226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.4152235226
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4201010901
Short name T405
Test name
Test status
Simulation time 229503046 ps
CPU time 1.39 seconds
Started Jun 09 01:35:47 PM PDT 24
Finished Jun 09 01:35:49 PM PDT 24
Peak memory 196940 kb
Host smart-08f0fc14-2cdc-4681-b1b3-8ca0d017bc5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201010901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4201010901
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2218123734
Short name T215
Test name
Test status
Simulation time 29528622 ps
CPU time 1.26 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:35:46 PM PDT 24
Peak memory 196352 kb
Host smart-20b96ded-b973-45c9-8148-073d39d9b76d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218123734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2218123734
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.645711422
Short name T96
Test name
Test status
Simulation time 57217068 ps
CPU time 1.08 seconds
Started Jun 09 01:35:43 PM PDT 24
Finished Jun 09 01:35:44 PM PDT 24
Peak memory 195820 kb
Host smart-02a3ec58-fde0-4714-8e31-c85321a48565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645711422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
645711422
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.57519623
Short name T202
Test name
Test status
Simulation time 201877045 ps
CPU time 1.25 seconds
Started Jun 09 01:35:38 PM PDT 24
Finished Jun 09 01:35:39 PM PDT 24
Peak memory 198072 kb
Host smart-e67f8b07-2d1a-4d06-837c-94cc029769ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57519623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.57519623
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1948174441
Short name T210
Test name
Test status
Simulation time 44645163 ps
CPU time 0.69 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:35:46 PM PDT 24
Peak memory 195504 kb
Host smart-3fe0bb6d-b82e-42b8-9ae5-ca508845ab15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948174441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1948174441
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2182550564
Short name T707
Test name
Test status
Simulation time 191894274 ps
CPU time 3.43 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:35:49 PM PDT 24
Peak memory 198008 kb
Host smart-99942d79-bd96-4c5b-b0b0-a5df802393ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182550564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2182550564
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1122895297
Short name T642
Test name
Test status
Simulation time 107368563 ps
CPU time 0.77 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:35:38 PM PDT 24
Peak memory 196012 kb
Host smart-d0a13908-e719-45f8-874d-023b24ce1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122895297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1122895297
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1176876790
Short name T195
Test name
Test status
Simulation time 283473112 ps
CPU time 1.23 seconds
Started Jun 09 01:35:37 PM PDT 24
Finished Jun 09 01:35:38 PM PDT 24
Peak memory 195652 kb
Host smart-019137f2-4b8f-4eb7-9a14-3b4bba90026e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176876790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1176876790
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.481980244
Short name T265
Test name
Test status
Simulation time 9270134919 ps
CPU time 64.31 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:36:49 PM PDT 24
Peak memory 198196 kb
Host smart-33241bac-6d24-4f9d-858c-093a680558ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481980244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.481980244
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4122897430
Short name T611
Test name
Test status
Simulation time 79732002 ps
CPU time 0.57 seconds
Started Jun 09 01:35:52 PM PDT 24
Finished Jun 09 01:35:53 PM PDT 24
Peak memory 194852 kb
Host smart-8353df7a-b34d-42e7-aaf8-0d021110657a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122897430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4122897430
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1347346504
Short name T287
Test name
Test status
Simulation time 55075167 ps
CPU time 0.61 seconds
Started Jun 09 01:35:43 PM PDT 24
Finished Jun 09 01:35:43 PM PDT 24
Peak memory 194740 kb
Host smart-789b56ec-a346-4cea-a5c0-66cf3148b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347346504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1347346504
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2512865650
Short name T429
Test name
Test status
Simulation time 719421575 ps
CPU time 22.87 seconds
Started Jun 09 01:35:42 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 196312 kb
Host smart-88d56d37-4128-4539-909c-91c590427dc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512865650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2512865650
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3979615611
Short name T529
Test name
Test status
Simulation time 87198385 ps
CPU time 0.6 seconds
Started Jun 09 01:35:47 PM PDT 24
Finished Jun 09 01:35:47 PM PDT 24
Peak memory 194236 kb
Host smart-1bb42fc3-d3be-42b1-964c-29d34ffc09bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979615611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3979615611
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.694690473
Short name T27
Test name
Test status
Simulation time 103094042 ps
CPU time 1.41 seconds
Started Jun 09 01:35:47 PM PDT 24
Finished Jun 09 01:35:49 PM PDT 24
Peak memory 196588 kb
Host smart-15ebbf66-fa43-431d-abb1-5fd0e9b75b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694690473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.694690473
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.559141682
Short name T415
Test name
Test status
Simulation time 501516181 ps
CPU time 1.88 seconds
Started Jun 09 01:35:47 PM PDT 24
Finished Jun 09 01:35:49 PM PDT 24
Peak memory 198028 kb
Host smart-33f77088-2b7b-4edf-a0f9-78568e43cad3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559141682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.559141682
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1788179194
Short name T179
Test name
Test status
Simulation time 776000941 ps
CPU time 3.86 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:35:49 PM PDT 24
Peak memory 197212 kb
Host smart-55a9b615-a3ea-4f3b-b4ed-f03368844306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788179194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1788179194
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4248466750
Short name T632
Test name
Test status
Simulation time 135831979 ps
CPU time 1.1 seconds
Started Jun 09 01:35:42 PM PDT 24
Finished Jun 09 01:35:43 PM PDT 24
Peak memory 195984 kb
Host smart-3a8496c5-f975-44dc-80c3-426a37106265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248466750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4248466750
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3586026097
Short name T709
Test name
Test status
Simulation time 34649572 ps
CPU time 1.27 seconds
Started Jun 09 01:35:45 PM PDT 24
Finished Jun 09 01:35:47 PM PDT 24
Peak memory 196652 kb
Host smart-fd25ad21-3be0-44bf-bd7a-4d81d71084ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586026097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3586026097
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2756462839
Short name T674
Test name
Test status
Simulation time 123028617 ps
CPU time 5.77 seconds
Started Jun 09 01:35:48 PM PDT 24
Finished Jun 09 01:35:54 PM PDT 24
Peak memory 197964 kb
Host smart-2b05d99c-4595-4e32-bb17-dcbffec857cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756462839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2756462839
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3175133356
Short name T533
Test name
Test status
Simulation time 78910814 ps
CPU time 0.99 seconds
Started Jun 09 01:35:42 PM PDT 24
Finished Jun 09 01:35:43 PM PDT 24
Peak memory 197204 kb
Host smart-b9a33b10-cda7-4cba-9e53-d4ee65ed6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175133356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3175133356
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3640765060
Short name T297
Test name
Test status
Simulation time 198579966 ps
CPU time 1.14 seconds
Started Jun 09 01:35:44 PM PDT 24
Finished Jun 09 01:35:45 PM PDT 24
Peak memory 195756 kb
Host smart-957b8b15-08db-4524-81a3-c2d31ff89a48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640765060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3640765060
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1068917707
Short name T276
Test name
Test status
Simulation time 1509049803 ps
CPU time 35.62 seconds
Started Jun 09 01:35:46 PM PDT 24
Finished Jun 09 01:36:22 PM PDT 24
Peak memory 198068 kb
Host smart-514afe4b-5ce2-4629-adc0-7c16ed3b3bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068917707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1068917707
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2765413555
Short name T56
Test name
Test status
Simulation time 90465693990 ps
CPU time 1881.61 seconds
Started Jun 09 01:35:55 PM PDT 24
Finished Jun 09 02:07:17 PM PDT 24
Peak memory 198276 kb
Host smart-b13cdfd3-fe26-400d-8c92-e111999ca6e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2765413555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2765413555
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3722151756
Short name T206
Test name
Test status
Simulation time 40746187 ps
CPU time 0.59 seconds
Started Jun 09 01:35:50 PM PDT 24
Finished Jun 09 01:35:51 PM PDT 24
Peak memory 193956 kb
Host smart-8116db9a-ff81-49e5-bd2a-2795abf47443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722151756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3722151756
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3212922130
Short name T570
Test name
Test status
Simulation time 78463058 ps
CPU time 0.72 seconds
Started Jun 09 01:35:54 PM PDT 24
Finished Jun 09 01:35:55 PM PDT 24
Peak memory 195408 kb
Host smart-9d107e3e-c0b0-4948-a020-6e1f79a8e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212922130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3212922130
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1246138665
Short name T559
Test name
Test status
Simulation time 479267446 ps
CPU time 8.41 seconds
Started Jun 09 01:35:51 PM PDT 24
Finished Jun 09 01:35:59 PM PDT 24
Peak memory 196300 kb
Host smart-a9ae95ca-08e3-4177-9ebf-ff6a98ef9d9e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246138665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1246138665
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2613698016
Short name T712
Test name
Test status
Simulation time 114361269 ps
CPU time 0.77 seconds
Started Jun 09 01:35:50 PM PDT 24
Finished Jun 09 01:35:51 PM PDT 24
Peak memory 196016 kb
Host smart-b44c9038-17b5-4ef3-8734-cdec3d19f3b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613698016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2613698016
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4066454265
Short name T308
Test name
Test status
Simulation time 234831888 ps
CPU time 0.96 seconds
Started Jun 09 01:35:51 PM PDT 24
Finished Jun 09 01:35:53 PM PDT 24
Peak memory 196036 kb
Host smart-614246ec-6f17-4d2e-ade5-fdaa65de3363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066454265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4066454265
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4011992582
Short name T692
Test name
Test status
Simulation time 636328765 ps
CPU time 1.81 seconds
Started Jun 09 01:35:54 PM PDT 24
Finished Jun 09 01:35:56 PM PDT 24
Peak memory 198056 kb
Host smart-562c0f3b-3285-4b3a-a1dc-48c1f72d5456
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011992582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4011992582
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3569408315
Short name T218
Test name
Test status
Simulation time 160750370 ps
CPU time 3.1 seconds
Started Jun 09 01:35:54 PM PDT 24
Finished Jun 09 01:35:57 PM PDT 24
Peak memory 195860 kb
Host smart-b96984c7-cbde-493b-ae19-bbfde696d83c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569408315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3569408315
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1678647947
Short name T352
Test name
Test status
Simulation time 72013745 ps
CPU time 0.89 seconds
Started Jun 09 01:35:51 PM PDT 24
Finished Jun 09 01:35:53 PM PDT 24
Peak memory 196548 kb
Host smart-d12e2e24-4308-4494-b1da-89e1b643e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678647947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1678647947
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4234929031
Short name T499
Test name
Test status
Simulation time 24533973 ps
CPU time 0.64 seconds
Started Jun 09 01:35:51 PM PDT 24
Finished Jun 09 01:35:52 PM PDT 24
Peak memory 195072 kb
Host smart-61d2b8d7-b6b7-4b37-9483-02c03b35cd04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234929031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4234929031
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1579084337
Short name T562
Test name
Test status
Simulation time 912519247 ps
CPU time 4.22 seconds
Started Jun 09 01:35:51 PM PDT 24
Finished Jun 09 01:35:56 PM PDT 24
Peak memory 198040 kb
Host smart-c8837a03-6b0e-483b-b809-9e12e47afc5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579084337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1579084337
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2457199882
Short name T686
Test name
Test status
Simulation time 260160663 ps
CPU time 1.4 seconds
Started Jun 09 01:35:50 PM PDT 24
Finished Jun 09 01:35:52 PM PDT 24
Peak memory 196760 kb
Host smart-1ece5494-6ecc-4112-be6b-f062c88d76e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457199882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2457199882
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3073443608
Short name T439
Test name
Test status
Simulation time 70084968 ps
CPU time 1.17 seconds
Started Jun 09 01:35:53 PM PDT 24
Finished Jun 09 01:35:55 PM PDT 24
Peak memory 196576 kb
Host smart-75e7b834-88fb-4509-a68f-8017e679304f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073443608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3073443608
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1310446839
Short name T255
Test name
Test status
Simulation time 14340387300 ps
CPU time 209.44 seconds
Started Jun 09 01:35:55 PM PDT 24
Finished Jun 09 01:39:25 PM PDT 24
Peak memory 198176 kb
Host smart-5dcfa273-8323-467f-b14e-320cfd062ba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310446839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1310446839
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2777333099
Short name T579
Test name
Test status
Simulation time 23847131 ps
CPU time 0.6 seconds
Started Jun 09 01:36:00 PM PDT 24
Finished Jun 09 01:36:01 PM PDT 24
Peak memory 194852 kb
Host smart-17631004-3e4e-4829-b77d-09de7bd4d9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777333099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2777333099
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1142888232
Short name T514
Test name
Test status
Simulation time 30813941 ps
CPU time 0.89 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:02 PM PDT 24
Peak memory 196640 kb
Host smart-c6c14954-cab9-42ae-86c3-124aa7fad40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142888232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1142888232
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2607131286
Short name T468
Test name
Test status
Simulation time 1910955468 ps
CPU time 24.83 seconds
Started Jun 09 01:35:59 PM PDT 24
Finished Jun 09 01:36:24 PM PDT 24
Peak memory 195496 kb
Host smart-c3cd49e7-3070-484c-9864-332d7bc5113f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607131286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2607131286
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4216337951
Short name T446
Test name
Test status
Simulation time 98744980 ps
CPU time 1.01 seconds
Started Jun 09 01:35:58 PM PDT 24
Finished Jun 09 01:36:00 PM PDT 24
Peak memory 196636 kb
Host smart-381ee200-8505-4219-acbd-349ee4c0834c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216337951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4216337951
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.458905034
Short name T392
Test name
Test status
Simulation time 31027450 ps
CPU time 0.83 seconds
Started Jun 09 01:36:00 PM PDT 24
Finished Jun 09 01:36:01 PM PDT 24
Peak memory 195436 kb
Host smart-ebdb4b9d-d72f-4c73-845f-e2fd2818ad63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458905034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.458905034
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2456807761
Short name T104
Test name
Test status
Simulation time 184570070 ps
CPU time 3.82 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 198032 kb
Host smart-27fae0e5-a7dd-4296-b25b-d524fe52f90a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456807761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2456807761
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1698523034
Short name T232
Test name
Test status
Simulation time 119411728 ps
CPU time 2.48 seconds
Started Jun 09 01:36:00 PM PDT 24
Finished Jun 09 01:36:02 PM PDT 24
Peak memory 197164 kb
Host smart-977434f5-b57a-4d19-a90a-d38faf135574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698523034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1698523034
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1134586132
Short name T150
Test name
Test status
Simulation time 45332114 ps
CPU time 0.77 seconds
Started Jun 09 01:35:54 PM PDT 24
Finished Jun 09 01:35:55 PM PDT 24
Peak memory 195576 kb
Host smart-ee6bd3ee-826a-475d-befb-df89998e7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134586132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1134586132
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1714727722
Short name T416
Test name
Test status
Simulation time 60347043 ps
CPU time 1.22 seconds
Started Jun 09 01:35:59 PM PDT 24
Finished Jun 09 01:36:01 PM PDT 24
Peak memory 197052 kb
Host smart-4f53fece-2cae-4331-9893-4b07a905c9c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714727722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1714727722
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.330473777
Short name T438
Test name
Test status
Simulation time 53988241 ps
CPU time 1.29 seconds
Started Jun 09 01:35:59 PM PDT 24
Finished Jun 09 01:36:00 PM PDT 24
Peak memory 198028 kb
Host smart-bb744089-ddb6-4380-962f-5a814df608e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330473777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.330473777
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1464443651
Short name T106
Test name
Test status
Simulation time 149747178 ps
CPU time 0.79 seconds
Started Jun 09 01:35:54 PM PDT 24
Finished Jun 09 01:35:55 PM PDT 24
Peak memory 196120 kb
Host smart-2f4ab3f8-11e0-4224-a729-251f8c8a07c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464443651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1464443651
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.58777531
Short name T550
Test name
Test status
Simulation time 51214077 ps
CPU time 1.34 seconds
Started Jun 09 01:35:49 PM PDT 24
Finished Jun 09 01:35:51 PM PDT 24
Peak memory 196312 kb
Host smart-5de88db1-6ef6-4c82-9ec2-0928baeec7be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58777531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.58777531
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2015270362
Short name T567
Test name
Test status
Simulation time 2203512877 ps
CPU time 40.2 seconds
Started Jun 09 01:35:58 PM PDT 24
Finished Jun 09 01:36:38 PM PDT 24
Peak memory 198092 kb
Host smart-984f43aa-b611-4a83-950e-cf8195cb2150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015270362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2015270362
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.593089600
Short name T425
Test name
Test status
Simulation time 37784021 ps
CPU time 0.59 seconds
Started Jun 09 01:36:04 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 194640 kb
Host smart-225f1280-8c07-460a-8579-e9d5c0914d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593089600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.593089600
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2516019439
Short name T347
Test name
Test status
Simulation time 25302578 ps
CPU time 0.61 seconds
Started Jun 09 01:35:59 PM PDT 24
Finished Jun 09 01:36:00 PM PDT 24
Peak memory 194680 kb
Host smart-2e58e330-0cd9-4b3f-9bf4-0dc46b617339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516019439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2516019439
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.781511574
Short name T333
Test name
Test status
Simulation time 2204711049 ps
CPU time 24.84 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:26 PM PDT 24
Peak memory 196972 kb
Host smart-783a78ca-2f0b-491f-8229-65bf46d62812
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781511574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.781511574
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3312330505
Short name T283
Test name
Test status
Simulation time 106413570 ps
CPU time 0.91 seconds
Started Jun 09 01:36:03 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 196920 kb
Host smart-9ed95cb1-638f-4d41-997a-63b0127b03e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312330505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3312330505
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1617433601
Short name T363
Test name
Test status
Simulation time 120256572 ps
CPU time 0.88 seconds
Started Jun 09 01:36:04 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 197612 kb
Host smart-2e15ba66-10c0-4e31-97b2-735d550c0000
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617433601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1617433601
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1499192701
Short name T505
Test name
Test status
Simulation time 1145500438 ps
CPU time 3.46 seconds
Started Jun 09 01:36:04 PM PDT 24
Finished Jun 09 01:36:08 PM PDT 24
Peak memory 198024 kb
Host smart-f30288d5-9251-4476-a6b0-166d3e810c61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499192701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1499192701
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2245168837
Short name T365
Test name
Test status
Simulation time 58902221 ps
CPU time 1.37 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 196636 kb
Host smart-e5b50040-c5d8-4975-8764-eaeba14766f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245168837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2245168837
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3705174571
Short name T336
Test name
Test status
Simulation time 47016387 ps
CPU time 0.8 seconds
Started Jun 09 01:35:59 PM PDT 24
Finished Jun 09 01:36:00 PM PDT 24
Peak memory 196216 kb
Host smart-343a7c3c-0f00-43b6-98a9-ecb2181785fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705174571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3705174571
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1244614193
Short name T148
Test name
Test status
Simulation time 60964179 ps
CPU time 1.05 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 196768 kb
Host smart-992f53f1-77cd-435d-b5c8-d7174e8f3fca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244614193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1244614193
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2404706286
Short name T387
Test name
Test status
Simulation time 160666473 ps
CPU time 3.39 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:04 PM PDT 24
Peak memory 198224 kb
Host smart-33b5db18-8dcd-495c-b34b-7261f8c1fae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404706286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2404706286
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1114404026
Short name T411
Test name
Test status
Simulation time 84088058 ps
CPU time 0.78 seconds
Started Jun 09 01:35:59 PM PDT 24
Finished Jun 09 01:36:00 PM PDT 24
Peak memory 195232 kb
Host smart-aa1ee609-07dc-4127-880d-443898f86966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114404026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1114404026
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3577993085
Short name T228
Test name
Test status
Simulation time 196176966 ps
CPU time 1.18 seconds
Started Jun 09 01:35:58 PM PDT 24
Finished Jun 09 01:35:59 PM PDT 24
Peak memory 196508 kb
Host smart-b7f65ce3-906c-4ba0-89bf-b0cf80287761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577993085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3577993085
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1138167513
Short name T421
Test name
Test status
Simulation time 3266255452 ps
CPU time 89.63 seconds
Started Jun 09 01:36:03 PM PDT 24
Finished Jun 09 01:37:33 PM PDT 24
Peak memory 198232 kb
Host smart-a0a7fc14-0dcd-436f-95f8-2c48a6d3c52e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138167513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1138167513
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3843217221
Short name T58
Test name
Test status
Simulation time 39239505405 ps
CPU time 1001.68 seconds
Started Jun 09 01:36:05 PM PDT 24
Finished Jun 09 01:52:47 PM PDT 24
Peak memory 198280 kb
Host smart-18c3099a-51c0-4287-9863-f4213d8bf3eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3843217221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3843217221
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.305399886
Short name T136
Test name
Test status
Simulation time 12323854 ps
CPU time 0.56 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 194640 kb
Host smart-e44b5725-4f8e-43f7-8b7a-c8d27cc334f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305399886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.305399886
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.199319978
Short name T702
Test name
Test status
Simulation time 251631800 ps
CPU time 0.81 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 195328 kb
Host smart-35619df4-5b68-46de-a890-adfa5a8d56ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199319978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.199319978
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4205361828
Short name T589
Test name
Test status
Simulation time 1536089392 ps
CPU time 8.67 seconds
Started Jun 09 01:36:00 PM PDT 24
Finished Jun 09 01:36:08 PM PDT 24
Peak memory 195576 kb
Host smart-4bd923f6-5fb2-4077-8c50-9a450fd28df0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205361828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4205361828
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4004331308
Short name T479
Test name
Test status
Simulation time 83641394 ps
CPU time 0.64 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 194396 kb
Host smart-3efb6fc1-8b58-45f8-a9c5-f5aea9d3bce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004331308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4004331308
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3294191227
Short name T50
Test name
Test status
Simulation time 194306240 ps
CPU time 1.03 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 196884 kb
Host smart-18f55743-f730-46a9-b3ee-1d208bfc2fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294191227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3294191227
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.684308586
Short name T246
Test name
Test status
Simulation time 85455759 ps
CPU time 3.32 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 198084 kb
Host smart-aa5f6b0a-b65b-4a59-9871-22af78697099
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684308586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.684308586
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3560359589
Short name T310
Test name
Test status
Simulation time 69995902 ps
CPU time 2.06 seconds
Started Jun 09 01:36:04 PM PDT 24
Finished Jun 09 01:36:06 PM PDT 24
Peak memory 195852 kb
Host smart-dc98516c-2cd5-44dd-9464-e2b65842fd22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560359589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3560359589
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3587916971
Short name T677
Test name
Test status
Simulation time 22155619 ps
CPU time 0.97 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 195952 kb
Host smart-607027da-5713-4ff7-8184-190a4af587c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587916971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3587916971
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4224966953
Short name T494
Test name
Test status
Simulation time 30605729 ps
CPU time 0.69 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 194420 kb
Host smart-5ce82c02-33c5-4fae-811a-8d0a304e80b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224966953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4224966953
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1154641983
Short name T321
Test name
Test status
Simulation time 277500471 ps
CPU time 3.52 seconds
Started Jun 09 01:36:06 PM PDT 24
Finished Jun 09 01:36:09 PM PDT 24
Peak memory 198016 kb
Host smart-f1fbf834-d2a9-45ce-b525-7771731ecd0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154641983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1154641983
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1036907316
Short name T177
Test name
Test status
Simulation time 67702564 ps
CPU time 0.69 seconds
Started Jun 09 01:36:03 PM PDT 24
Finished Jun 09 01:36:04 PM PDT 24
Peak memory 194200 kb
Host smart-cc05697e-af45-4a53-9ab2-84e3ebfd855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036907316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1036907316
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2806334803
Short name T334
Test name
Test status
Simulation time 257859385 ps
CPU time 0.81 seconds
Started Jun 09 01:36:06 PM PDT 24
Finished Jun 09 01:36:07 PM PDT 24
Peak memory 195484 kb
Host smart-1c6869ed-fca1-4e8f-9e1d-2073a5091734
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806334803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2806334803
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2744425682
Short name T370
Test name
Test status
Simulation time 33349810522 ps
CPU time 172.38 seconds
Started Jun 09 01:36:01 PM PDT 24
Finished Jun 09 01:38:54 PM PDT 24
Peak memory 198200 kb
Host smart-9cbf9a39-926d-4fd2-8940-ffa0084c92ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744425682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2744425682
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4078821540
Short name T131
Test name
Test status
Simulation time 44261094 ps
CPU time 0.56 seconds
Started Jun 09 01:36:07 PM PDT 24
Finished Jun 09 01:36:08 PM PDT 24
Peak memory 193960 kb
Host smart-1b57cf01-f881-4146-8b73-3acc74f28b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078821540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4078821540
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4057212504
Short name T101
Test name
Test status
Simulation time 22763305 ps
CPU time 0.75 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 195468 kb
Host smart-d42737c5-0f54-495c-a507-0f9907c5662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057212504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4057212504
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1821534868
Short name T28
Test name
Test status
Simulation time 12801430740 ps
CPU time 26.48 seconds
Started Jun 09 01:36:06 PM PDT 24
Finished Jun 09 01:36:33 PM PDT 24
Peak memory 197008 kb
Host smart-707d6526-0253-42f9-9509-24dbcfb86ca6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821534868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1821534868
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.697408778
Short name T460
Test name
Test status
Simulation time 63595640 ps
CPU time 1.01 seconds
Started Jun 09 01:36:08 PM PDT 24
Finished Jun 09 01:36:09 PM PDT 24
Peak memory 197936 kb
Host smart-e4972ea0-8948-4d59-9186-35d2a568fe98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697408778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.697408778
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2661834239
Short name T462
Test name
Test status
Simulation time 49880214 ps
CPU time 1.29 seconds
Started Jun 09 01:36:08 PM PDT 24
Finished Jun 09 01:36:09 PM PDT 24
Peak memory 195844 kb
Host smart-f7ded73f-3103-4608-b1fe-0b89f6855339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661834239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2661834239
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2451785852
Short name T94
Test name
Test status
Simulation time 373472282 ps
CPU time 1.99 seconds
Started Jun 09 01:36:07 PM PDT 24
Finished Jun 09 01:36:10 PM PDT 24
Peak memory 196384 kb
Host smart-1d26f64f-0e4f-4a2a-ad64-025f40920867
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451785852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2451785852
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1013445547
Short name T535
Test name
Test status
Simulation time 302664445 ps
CPU time 2.45 seconds
Started Jun 09 01:36:08 PM PDT 24
Finished Jun 09 01:36:10 PM PDT 24
Peak memory 197028 kb
Host smart-19fc5b01-bad0-41e6-b268-35e6a4177a8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013445547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1013445547
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1265275015
Short name T527
Test name
Test status
Simulation time 20939111 ps
CPU time 0.9 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:03 PM PDT 24
Peak memory 196708 kb
Host smart-2afe4044-c110-4494-850b-7e357e2029fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265275015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1265275015
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3388725787
Short name T521
Test name
Test status
Simulation time 75110773 ps
CPU time 1.42 seconds
Started Jun 09 01:36:02 PM PDT 24
Finished Jun 09 01:36:04 PM PDT 24
Peak memory 195888 kb
Host smart-382dd476-0f48-4dc5-8e5c-181dc09c38d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388725787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3388725787
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.795390876
Short name T532
Test name
Test status
Simulation time 72242080 ps
CPU time 3.29 seconds
Started Jun 09 01:36:08 PM PDT 24
Finished Jun 09 01:36:11 PM PDT 24
Peak memory 198012 kb
Host smart-cfb9a807-e71f-4069-a545-0ccc48b75009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795390876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.795390876
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2274782082
Short name T693
Test name
Test status
Simulation time 38204743 ps
CPU time 0.87 seconds
Started Jun 09 01:36:04 PM PDT 24
Finished Jun 09 01:36:05 PM PDT 24
Peak memory 195500 kb
Host smart-49bc8a04-2649-4b91-beb3-1b9d15d2c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274782082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2274782082
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.704111377
Short name T426
Test name
Test status
Simulation time 143281448 ps
CPU time 1.33 seconds
Started Jun 09 01:36:05 PM PDT 24
Finished Jun 09 01:36:07 PM PDT 24
Peak memory 196908 kb
Host smart-2ce67ecc-77a9-4909-8a14-1d8ba040fae3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704111377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.704111377
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2719830907
Short name T6
Test name
Test status
Simulation time 2212308630 ps
CPU time 23.21 seconds
Started Jun 09 01:36:07 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 198096 kb
Host smart-9e46817e-f26b-456a-9822-abaac85d6418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719830907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2719830907
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2763900698
Short name T304
Test name
Test status
Simulation time 26843328 ps
CPU time 0.58 seconds
Started Jun 09 01:34:31 PM PDT 24
Finished Jun 09 01:34:32 PM PDT 24
Peak memory 194124 kb
Host smart-eb10fb21-6093-4669-b9c5-ceb8903b9007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763900698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2763900698
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.23104585
Short name T590
Test name
Test status
Simulation time 127497618 ps
CPU time 0.88 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:23 PM PDT 24
Peak memory 195368 kb
Host smart-a2fc5843-b1f4-47b5-9e4c-431fb23acfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23104585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.23104585
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3306764620
Short name T432
Test name
Test status
Simulation time 1351870272 ps
CPU time 17.78 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:40 PM PDT 24
Peak memory 197180 kb
Host smart-84974819-8bf9-4c76-8a8c-f72a1a3d1761
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306764620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3306764620
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3628643888
Short name T299
Test name
Test status
Simulation time 152085370 ps
CPU time 0.82 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:24 PM PDT 24
Peak memory 196164 kb
Host smart-9fa88515-7b79-423f-ada1-dfbbed5a2728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628643888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3628643888
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1755620737
Short name T455
Test name
Test status
Simulation time 41052822 ps
CPU time 1.13 seconds
Started Jun 09 01:34:24 PM PDT 24
Finished Jun 09 01:34:25 PM PDT 24
Peak memory 196900 kb
Host smart-35de8ef5-45bb-49a2-96d9-cc1166c3c09b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755620737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1755620737
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1772586096
Short name T198
Test name
Test status
Simulation time 30290714 ps
CPU time 1.36 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:24 PM PDT 24
Peak memory 196776 kb
Host smart-19cacc44-f850-4167-aaf4-7576af95df94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772586096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1772586096
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.966580983
Short name T440
Test name
Test status
Simulation time 367058702 ps
CPU time 2.13 seconds
Started Jun 09 01:34:23 PM PDT 24
Finished Jun 09 01:34:26 PM PDT 24
Peak memory 196804 kb
Host smart-165087b1-2f90-49b8-ad6a-eda847435764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966580983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.966580983
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1710273056
Short name T385
Test name
Test status
Simulation time 105366821 ps
CPU time 0.82 seconds
Started Jun 09 01:34:20 PM PDT 24
Finished Jun 09 01:34:21 PM PDT 24
Peak memory 196640 kb
Host smart-ab019aab-9f98-471f-a16d-e268a44e6faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710273056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1710273056
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2640909674
Short name T688
Test name
Test status
Simulation time 173211031 ps
CPU time 0.71 seconds
Started Jun 09 01:34:21 PM PDT 24
Finished Jun 09 01:34:23 PM PDT 24
Peak memory 195492 kb
Host smart-b0492467-44c1-4687-be9a-41e0407fc9ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640909674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2640909674
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3385991402
Short name T175
Test name
Test status
Simulation time 384003488 ps
CPU time 6.28 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 198008 kb
Host smart-6dffc139-6b4a-4132-be81-410b1a5f948d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385991402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3385991402
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3506055179
Short name T48
Test name
Test status
Simulation time 144780718 ps
CPU time 0.82 seconds
Started Jun 09 01:34:26 PM PDT 24
Finished Jun 09 01:34:27 PM PDT 24
Peak memory 213816 kb
Host smart-506599d5-f91c-46a1-bc5a-73fe40ae2eba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506055179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3506055179
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3136546760
Short name T447
Test name
Test status
Simulation time 165816561 ps
CPU time 1.17 seconds
Started Jun 09 01:34:22 PM PDT 24
Finished Jun 09 01:34:23 PM PDT 24
Peak memory 196568 kb
Host smart-d6ec4395-e364-4210-9ee3-11f477f5aa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136546760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3136546760
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3513083702
Short name T689
Test name
Test status
Simulation time 234422059 ps
CPU time 1.11 seconds
Started Jun 09 01:34:21 PM PDT 24
Finished Jun 09 01:34:22 PM PDT 24
Peak memory 195824 kb
Host smart-3a33a7b1-9b6a-46f4-8a9a-abd1afccd555
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513083702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3513083702
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3638191214
Short name T482
Test name
Test status
Simulation time 4890393862 ps
CPU time 69.8 seconds
Started Jun 09 01:34:23 PM PDT 24
Finished Jun 09 01:35:33 PM PDT 24
Peak memory 198356 kb
Host smart-4c2a5389-a57b-49eb-9289-0f9d5175826e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638191214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3638191214
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.221982254
Short name T375
Test name
Test status
Simulation time 34487238 ps
CPU time 0.59 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:14 PM PDT 24
Peak memory 194152 kb
Host smart-3eef6dfa-85b2-4632-aa4d-18a6a2c179c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221982254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.221982254
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2990773534
Short name T678
Test name
Test status
Simulation time 29067144 ps
CPU time 0.69 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 194292 kb
Host smart-132980fa-2554-43aa-8d26-9b7d31967183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990773534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2990773534
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.366162705
Short name T526
Test name
Test status
Simulation time 742564836 ps
CPU time 12.13 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:36:25 PM PDT 24
Peak memory 198220 kb
Host smart-661d132f-f9b6-4c6a-be7d-db9cd7a5cbf6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366162705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.366162705
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.4032859630
Short name T324
Test name
Test status
Simulation time 49725781 ps
CPU time 0.86 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 196104 kb
Host smart-fa123489-c735-46fb-b5c9-fbfbc71417ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032859630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.4032859630
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1662781028
Short name T263
Test name
Test status
Simulation time 70829910 ps
CPU time 0.79 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 195716 kb
Host smart-98d0cd25-01fe-4fb9-a0fe-974d74a52cf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662781028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1662781028
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2540322847
Short name T345
Test name
Test status
Simulation time 342570675 ps
CPU time 3.17 seconds
Started Jun 09 01:36:11 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 198144 kb
Host smart-305c6e9e-d687-4b20-97fa-ba2b42de600a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540322847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2540322847
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2018703004
Short name T194
Test name
Test status
Simulation time 298186390 ps
CPU time 1.68 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 196656 kb
Host smart-2d453278-3268-485e-a5c6-150e2f33334d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018703004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2018703004
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1342295414
Short name T243
Test name
Test status
Simulation time 28512549 ps
CPU time 0.79 seconds
Started Jun 09 01:36:07 PM PDT 24
Finished Jun 09 01:36:08 PM PDT 24
Peak memory 196164 kb
Host smart-961f28a3-e19a-4b89-a2ab-f479b847b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342295414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1342295414
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2308981476
Short name T259
Test name
Test status
Simulation time 38975882 ps
CPU time 0.96 seconds
Started Jun 09 01:36:10 PM PDT 24
Finished Jun 09 01:36:11 PM PDT 24
Peak memory 195852 kb
Host smart-a65c6d89-d9d6-4dab-8696-fba9fb5783fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308981476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2308981476
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1112056541
Short name T435
Test name
Test status
Simulation time 268670316 ps
CPU time 4.35 seconds
Started Jun 09 01:36:18 PM PDT 24
Finished Jun 09 01:36:23 PM PDT 24
Peak memory 198092 kb
Host smart-b8034a38-4b51-42c7-96f3-d8f46ed2388c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112056541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1112056541
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2245876639
Short name T395
Test name
Test status
Simulation time 162296763 ps
CPU time 0.94 seconds
Started Jun 09 01:36:09 PM PDT 24
Finished Jun 09 01:36:10 PM PDT 24
Peak memory 197264 kb
Host smart-d7751d06-815f-4d00-86f1-b91e0ed3c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245876639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2245876639
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2033196492
Short name T192
Test name
Test status
Simulation time 84649825 ps
CPU time 0.7 seconds
Started Jun 09 01:36:07 PM PDT 24
Finished Jun 09 01:36:08 PM PDT 24
Peak memory 194240 kb
Host smart-e3561c23-cfa7-41bc-9d09-feed9422febb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033196492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2033196492
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1659431713
Short name T484
Test name
Test status
Simulation time 7244441231 ps
CPU time 83.29 seconds
Started Jun 09 01:36:16 PM PDT 24
Finished Jun 09 01:37:40 PM PDT 24
Peak memory 198200 kb
Host smart-957383e0-78ff-4a53-b45a-242d38226d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659431713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1659431713
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1459783406
Short name T605
Test name
Test status
Simulation time 21162335 ps
CPU time 0.57 seconds
Started Jun 09 01:36:15 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 193952 kb
Host smart-d030e73b-afd2-4e3c-9a69-6572adaa0135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459783406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1459783406
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.238630351
Short name T466
Test name
Test status
Simulation time 104749419 ps
CPU time 0.93 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 196652 kb
Host smart-1df7e60a-81cf-4545-9a5b-ff0e5d27a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238630351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.238630351
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.837343962
Short name T697
Test name
Test status
Simulation time 700653312 ps
CPU time 18.82 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:34 PM PDT 24
Peak memory 196304 kb
Host smart-b4adbc5c-da78-45bd-921d-30fe2a0a457d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837343962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.837343962
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3470284751
Short name T225
Test name
Test status
Simulation time 183087487 ps
CPU time 0.9 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:36:14 PM PDT 24
Peak memory 197268 kb
Host smart-31ce20d5-c538-4382-9c01-5d5bd43b2b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470284751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3470284751
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4054491348
Short name T372
Test name
Test status
Simulation time 27355509 ps
CPU time 0.91 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:14 PM PDT 24
Peak memory 196760 kb
Host smart-968d1e0e-f09e-4ccd-aaa9-da7bb9f8ee81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054491348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4054491348
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.156850956
Short name T427
Test name
Test status
Simulation time 75547200 ps
CPU time 2.88 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 198060 kb
Host smart-5d9a16c1-559a-4352-91cb-686158b5746d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156850956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.156850956
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3125985268
Short name T303
Test name
Test status
Simulation time 460244149 ps
CPU time 3.55 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 195832 kb
Host smart-62e32027-2e2e-4dd7-adcf-033deb14a077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125985268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3125985268
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2688556687
Short name T100
Test name
Test status
Simulation time 31212912 ps
CPU time 0.68 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:36:13 PM PDT 24
Peak memory 194432 kb
Host smart-e5375f3f-2cb6-45f4-ad2e-bb5809b99f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688556687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2688556687
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2600234427
Short name T380
Test name
Test status
Simulation time 201034019 ps
CPU time 1.22 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:36:13 PM PDT 24
Peak memory 196760 kb
Host smart-ce090d51-9489-4997-8ba0-dbcdb4afaf46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600234427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2600234427
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.4043586957
Short name T661
Test name
Test status
Simulation time 884517484 ps
CPU time 5.78 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 198004 kb
Host smart-1916f7a6-3e0c-4da5-832b-751333aec0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043586957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.4043586957
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3701070054
Short name T481
Test name
Test status
Simulation time 172092166 ps
CPU time 1.01 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 195408 kb
Host smart-06fdec3d-accd-4542-8b8b-c16b73fb750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701070054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3701070054
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2766540506
Short name T588
Test name
Test status
Simulation time 175108776 ps
CPU time 0.9 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:36:13 PM PDT 24
Peak memory 197184 kb
Host smart-8ecad9b9-a78f-4838-a6e9-19e6d52f89f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766540506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2766540506
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3732159915
Short name T389
Test name
Test status
Simulation time 84059367068 ps
CPU time 257.8 seconds
Started Jun 09 01:36:12 PM PDT 24
Finished Jun 09 01:40:30 PM PDT 24
Peak memory 198228 kb
Host smart-1738a97f-f879-4c82-9c46-5ba61124a4ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732159915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3732159915
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.183668615
Short name T652
Test name
Test status
Simulation time 25398345059 ps
CPU time 130.67 seconds
Started Jun 09 01:36:11 PM PDT 24
Finished Jun 09 01:38:22 PM PDT 24
Peak memory 198264 kb
Host smart-663d100f-b825-4faa-81dc-e748db990099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=183668615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.183668615
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1853498969
Short name T509
Test name
Test status
Simulation time 102380951 ps
CPU time 0.56 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:13 PM PDT 24
Peak memory 193928 kb
Host smart-d2250b03-c331-43a2-b03c-0b6c4bb42a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853498969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1853498969
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3431444846
Short name T113
Test name
Test status
Simulation time 45738184 ps
CPU time 0.94 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 196688 kb
Host smart-d0889c08-4204-4421-8959-d8ae4230b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431444846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3431444846
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1320833136
Short name T295
Test name
Test status
Simulation time 329037495 ps
CPU time 9.5 seconds
Started Jun 09 01:36:16 PM PDT 24
Finished Jun 09 01:36:26 PM PDT 24
Peak memory 195548 kb
Host smart-9211b683-6fc3-46d8-8fe9-3157d6a09a54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320833136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1320833136
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.394659097
Short name T356
Test name
Test status
Simulation time 67622247 ps
CPU time 0.83 seconds
Started Jun 09 01:36:16 PM PDT 24
Finished Jun 09 01:36:18 PM PDT 24
Peak memory 196156 kb
Host smart-37eb2046-3895-4f2c-8a13-a86dc06ea7bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394659097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.394659097
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4102353496
Short name T374
Test name
Test status
Simulation time 44553889 ps
CPU time 0.82 seconds
Started Jun 09 01:36:16 PM PDT 24
Finished Jun 09 01:36:17 PM PDT 24
Peak memory 195744 kb
Host smart-adf05deb-f254-40bf-a7e7-77832c609487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102353496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4102353496
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3401741376
Short name T289
Test name
Test status
Simulation time 381492736 ps
CPU time 2.03 seconds
Started Jun 09 01:36:16 PM PDT 24
Finished Jun 09 01:36:18 PM PDT 24
Peak memory 198072 kb
Host smart-7ff3b93a-8d03-4762-bf21-43824afdd5a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401741376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3401741376
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.953103664
Short name T547
Test name
Test status
Simulation time 65536908 ps
CPU time 1.44 seconds
Started Jun 09 01:36:15 PM PDT 24
Finished Jun 09 01:36:17 PM PDT 24
Peak memory 195892 kb
Host smart-7f0adc86-0484-4bc3-8975-ba999abc25e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953103664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
953103664
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.562408163
Short name T286
Test name
Test status
Simulation time 586089970 ps
CPU time 1.38 seconds
Started Jun 09 01:36:16 PM PDT 24
Finished Jun 09 01:36:18 PM PDT 24
Peak memory 196848 kb
Host smart-327f3d61-c68e-4b5c-a683-c03d3c5e8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562408163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.562408163
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1329739242
Short name T700
Test name
Test status
Simulation time 31653509 ps
CPU time 0.75 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 196256 kb
Host smart-f9e5f709-eae8-493b-b849-866bc97b09d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329739242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1329739242
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2241098625
Short name T431
Test name
Test status
Simulation time 554409649 ps
CPU time 5.9 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 197112 kb
Host smart-af61d8d1-eb62-416b-ac75-0dcc00de533b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241098625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2241098625
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2169695018
Short name T534
Test name
Test status
Simulation time 69206825 ps
CPU time 1.22 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:14 PM PDT 24
Peak memory 195500 kb
Host smart-28d97c05-8c34-4190-a9ca-40f17fddddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169695018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2169695018
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3083745198
Short name T307
Test name
Test status
Simulation time 62692835 ps
CPU time 1.09 seconds
Started Jun 09 01:36:13 PM PDT 24
Finished Jun 09 01:36:15 PM PDT 24
Peak memory 195568 kb
Host smart-ab952e8b-084b-4758-9168-042036981b99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083745198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3083745198
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2132222927
Short name T541
Test name
Test status
Simulation time 6224140922 ps
CPU time 72.84 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:37:35 PM PDT 24
Peak memory 198248 kb
Host smart-f7c41e40-8eea-491b-a177-ce93dae3940f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132222927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2132222927
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.572357585
Short name T97
Test name
Test status
Simulation time 20421521 ps
CPU time 0.57 seconds
Started Jun 09 01:36:24 PM PDT 24
Finished Jun 09 01:36:25 PM PDT 24
Peak memory 193920 kb
Host smart-f5673808-41df-4192-ae79-171c6e9e0da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572357585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.572357585
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.562984585
Short name T176
Test name
Test status
Simulation time 15971324 ps
CPU time 0.64 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:18 PM PDT 24
Peak memory 194792 kb
Host smart-fb051c62-9570-4e29-937c-c3ae7a1dab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562984585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.562984585
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1252954759
Short name T410
Test name
Test status
Simulation time 414686350 ps
CPU time 21.16 seconds
Started Jun 09 01:36:19 PM PDT 24
Finished Jun 09 01:36:40 PM PDT 24
Peak memory 196912 kb
Host smart-428180ff-4463-4056-954c-f7846dd3d438
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252954759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1252954759
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2949221502
Short name T353
Test name
Test status
Simulation time 94597888 ps
CPU time 1 seconds
Started Jun 09 01:36:18 PM PDT 24
Finished Jun 09 01:36:19 PM PDT 24
Peak memory 197352 kb
Host smart-1149c889-5294-4909-951e-b128ae8565be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949221502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2949221502
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2879115194
Short name T396
Test name
Test status
Simulation time 115689922 ps
CPU time 1.06 seconds
Started Jun 09 01:36:18 PM PDT 24
Finished Jun 09 01:36:19 PM PDT 24
Peak memory 196608 kb
Host smart-0e45c2db-7bec-4f90-9a7a-33c2585fdfb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879115194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2879115194
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.348343956
Short name T593
Test name
Test status
Simulation time 136310094 ps
CPU time 1.59 seconds
Started Jun 09 01:36:18 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 196496 kb
Host smart-bb24ef2e-4610-40b8-862e-f2df1f4f8486
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348343956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.348343956
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1770227538
Short name T539
Test name
Test status
Simulation time 374810491 ps
CPU time 3.07 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 197232 kb
Host smart-b5f0da75-5005-4270-8d42-22c381dd6a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770227538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1770227538
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3196110688
Short name T314
Test name
Test status
Simulation time 56926011 ps
CPU time 0.74 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:18 PM PDT 24
Peak memory 196212 kb
Host smart-8892e480-bb18-4792-a1e4-55644cdc7cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196110688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3196110688
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1223516648
Short name T685
Test name
Test status
Simulation time 26571235 ps
CPU time 1 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:19 PM PDT 24
Peak memory 196028 kb
Host smart-0719da65-1c0a-4832-82f6-beaee600639a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223516648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1223516648
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2102764319
Short name T169
Test name
Test status
Simulation time 152687704 ps
CPU time 1.83 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:20 PM PDT 24
Peak memory 197904 kb
Host smart-3fd17993-384a-4d9e-8b90-d00d37b6fef3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102764319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2102764319
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1057126155
Short name T138
Test name
Test status
Simulation time 38360907 ps
CPU time 1.1 seconds
Started Jun 09 01:36:14 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 195772 kb
Host smart-fc457f90-9223-40a8-bd12-b448e2941060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057126155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1057126155
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.344882112
Short name T682
Test name
Test status
Simulation time 144120690 ps
CPU time 0.83 seconds
Started Jun 09 01:36:17 PM PDT 24
Finished Jun 09 01:36:19 PM PDT 24
Peak memory 195384 kb
Host smart-822f80ad-6677-40a0-acd9-ec5d9c4366e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344882112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.344882112
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4215430060
Short name T497
Test name
Test status
Simulation time 5146745393 ps
CPU time 137.14 seconds
Started Jun 09 01:36:19 PM PDT 24
Finished Jun 09 01:38:37 PM PDT 24
Peak memory 198244 kb
Host smart-122b89e2-1868-434c-9953-07c7d3e82172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215430060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4215430060
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.435252993
Short name T57
Test name
Test status
Simulation time 55453090328 ps
CPU time 1755.39 seconds
Started Jun 09 01:36:22 PM PDT 24
Finished Jun 09 02:05:38 PM PDT 24
Peak memory 198256 kb
Host smart-6edc6eaa-1c03-4041-8edb-143f8d5249dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=435252993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.435252993
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3749201529
Short name T309
Test name
Test status
Simulation time 22535535 ps
CPU time 0.6 seconds
Started Jun 09 01:36:28 PM PDT 24
Finished Jun 09 01:36:29 PM PDT 24
Peak memory 194172 kb
Host smart-71800b6e-ab5b-44c3-981b-255270d722bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749201529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3749201529
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3632163591
Short name T350
Test name
Test status
Simulation time 64727741 ps
CPU time 0.9 seconds
Started Jun 09 01:36:22 PM PDT 24
Finished Jun 09 01:36:24 PM PDT 24
Peak memory 196276 kb
Host smart-f9da87aa-9363-4b6d-a939-54a718be7116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632163591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3632163591
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.577981553
Short name T399
Test name
Test status
Simulation time 261363519 ps
CPU time 8.1 seconds
Started Jun 09 01:36:23 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 196280 kb
Host smart-f085d0a5-3dfc-4bfb-b404-0d43753a8903
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577981553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.577981553
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3665406719
Short name T710
Test name
Test status
Simulation time 457803622 ps
CPU time 1.03 seconds
Started Jun 09 01:36:22 PM PDT 24
Finished Jun 09 01:36:23 PM PDT 24
Peak memory 197528 kb
Host smart-4ffb6d9a-a820-4f49-836b-9f52d9ca1fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665406719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3665406719
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.278992423
Short name T229
Test name
Test status
Simulation time 36739865 ps
CPU time 1.04 seconds
Started Jun 09 01:36:23 PM PDT 24
Finished Jun 09 01:36:24 PM PDT 24
Peak memory 196040 kb
Host smart-9ab6496a-1fa1-47dc-bc37-8afcc23f5977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278992423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.278992423
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3340674892
Short name T320
Test name
Test status
Simulation time 30666107 ps
CPU time 1.16 seconds
Started Jun 09 01:36:23 PM PDT 24
Finished Jun 09 01:36:24 PM PDT 24
Peak memory 196552 kb
Host smart-5c1af669-6ef3-421e-b941-2e96dc773c00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340674892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3340674892
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1471539762
Short name T434
Test name
Test status
Simulation time 230816555 ps
CPU time 4.01 seconds
Started Jun 09 01:36:21 PM PDT 24
Finished Jun 09 01:36:25 PM PDT 24
Peak memory 196964 kb
Host smart-90b05d7e-7c78-43d1-a438-c907eee7152c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471539762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1471539762
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3744453395
Short name T233
Test name
Test status
Simulation time 98396464 ps
CPU time 0.79 seconds
Started Jun 09 01:36:25 PM PDT 24
Finished Jun 09 01:36:26 PM PDT 24
Peak memory 196240 kb
Host smart-d6d86a5f-b4b8-4514-9a79-7fb8b1187de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744453395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3744453395
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2029040336
Short name T183
Test name
Test status
Simulation time 110481856 ps
CPU time 1.09 seconds
Started Jun 09 01:36:22 PM PDT 24
Finished Jun 09 01:36:24 PM PDT 24
Peak memory 196760 kb
Host smart-6c00d3c4-8c1c-4fe4-be91-bece5eef1800
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029040336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2029040336
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3200650745
Short name T454
Test name
Test status
Simulation time 367411795 ps
CPU time 6.24 seconds
Started Jun 09 01:36:21 PM PDT 24
Finished Jun 09 01:36:28 PM PDT 24
Peak memory 197944 kb
Host smart-fb242962-d793-4ed4-ae31-94e1dbcebd76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200650745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3200650745
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.4057132270
Short name T302
Test name
Test status
Simulation time 70317234 ps
CPU time 1.23 seconds
Started Jun 09 01:36:23 PM PDT 24
Finished Jun 09 01:36:25 PM PDT 24
Peak memory 195804 kb
Host smart-962f10a1-c63b-4a14-9aee-68bf23c90e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057132270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.4057132270
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2373770954
Short name T422
Test name
Test status
Simulation time 529863264 ps
CPU time 1.11 seconds
Started Jun 09 01:36:22 PM PDT 24
Finished Jun 09 01:36:23 PM PDT 24
Peak memory 195732 kb
Host smart-86e93ea5-ef1d-459d-93a0-debbfbc7dbf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373770954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2373770954
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3489703555
Short name T551
Test name
Test status
Simulation time 5828181418 ps
CPU time 111.21 seconds
Started Jun 09 01:36:23 PM PDT 24
Finished Jun 09 01:38:14 PM PDT 24
Peak memory 198224 kb
Host smart-0bea13a3-9cc1-4ff7-b946-b2b3babb27a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489703555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3489703555
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3032517032
Short name T711
Test name
Test status
Simulation time 57353642 ps
CPU time 0.58 seconds
Started Jun 09 01:36:29 PM PDT 24
Finished Jun 09 01:36:30 PM PDT 24
Peak memory 194160 kb
Host smart-e7038b07-f94d-43be-8d50-e54834f4b412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032517032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3032517032
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.827433569
Short name T486
Test name
Test status
Simulation time 29331473 ps
CPU time 0.72 seconds
Started Jun 09 01:36:29 PM PDT 24
Finished Jun 09 01:36:30 PM PDT 24
Peak memory 194200 kb
Host smart-620d9313-d06d-4318-85aa-f7f8d1cb275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827433569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.827433569
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3792378236
Short name T597
Test name
Test status
Simulation time 1678896006 ps
CPU time 12.34 seconds
Started Jun 09 01:36:28 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 197368 kb
Host smart-9f04b8da-c08f-47a0-bc5f-aa6e40e108da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792378236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3792378236
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.372147580
Short name T445
Test name
Test status
Simulation time 270916088 ps
CPU time 1.02 seconds
Started Jun 09 01:36:30 PM PDT 24
Finished Jun 09 01:36:32 PM PDT 24
Peak memory 197392 kb
Host smart-6a1d326b-73bd-4c6a-be43-440d199c5b96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372147580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.372147580
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2775778296
Short name T248
Test name
Test status
Simulation time 247999964 ps
CPU time 0.8 seconds
Started Jun 09 01:36:32 PM PDT 24
Finished Jun 09 01:36:33 PM PDT 24
Peak memory 195704 kb
Host smart-f3bb7a9a-8986-47d9-a84c-7c8f2c6073e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775778296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2775778296
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.373505492
Short name T672
Test name
Test status
Simulation time 270163052 ps
CPU time 2.81 seconds
Started Jun 09 01:36:30 PM PDT 24
Finished Jun 09 01:36:33 PM PDT 24
Peak memory 197080 kb
Host smart-92c2cc86-5dd3-468c-bc15-e652e2918ee9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373505492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.373505492
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3240879703
Short name T99
Test name
Test status
Simulation time 171432257 ps
CPU time 3.28 seconds
Started Jun 09 01:36:30 PM PDT 24
Finished Jun 09 01:36:34 PM PDT 24
Peak memory 197292 kb
Host smart-ea25b66f-ecae-4064-a01d-ba053edda6cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240879703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3240879703
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1046132444
Short name T483
Test name
Test status
Simulation time 273837114 ps
CPU time 1.18 seconds
Started Jun 09 01:36:28 PM PDT 24
Finished Jun 09 01:36:30 PM PDT 24
Peak memory 195888 kb
Host smart-f775c389-b895-46de-9b9a-b0d50f0ea63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046132444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1046132444
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2365991573
Short name T114
Test name
Test status
Simulation time 232195502 ps
CPU time 1.2 seconds
Started Jun 09 01:36:29 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 195792 kb
Host smart-7f45cef4-f102-4ab6-a8f3-829d0a6f45bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365991573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2365991573
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3413060392
Short name T515
Test name
Test status
Simulation time 102750133 ps
CPU time 1.55 seconds
Started Jun 09 01:36:29 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 198008 kb
Host smart-760c5b00-e3f5-4341-8da8-0596e43836ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413060392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3413060392
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.341717890
Short name T560
Test name
Test status
Simulation time 978561797 ps
CPU time 0.98 seconds
Started Jun 09 01:36:31 PM PDT 24
Finished Jun 09 01:36:32 PM PDT 24
Peak memory 197096 kb
Host smart-3257517e-1647-43cb-be2c-3087f9fc3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341717890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.341717890
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.760877088
Short name T648
Test name
Test status
Simulation time 26821079 ps
CPU time 0.82 seconds
Started Jun 09 01:36:30 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 195236 kb
Host smart-19baf226-1b5a-4113-9460-13612ff8945e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760877088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.760877088
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3963759508
Short name T338
Test name
Test status
Simulation time 30770320837 ps
CPU time 62.48 seconds
Started Jun 09 01:36:28 PM PDT 24
Finished Jun 09 01:37:31 PM PDT 24
Peak memory 198216 kb
Host smart-3a1a8d2c-78dc-47ef-b84c-3555bb09e757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963759508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3963759508
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.982843736
Short name T699
Test name
Test status
Simulation time 21027129 ps
CPU time 0.55 seconds
Started Jun 09 01:36:33 PM PDT 24
Finished Jun 09 01:36:35 PM PDT 24
Peak memory 193952 kb
Host smart-55176056-4fbc-4a7f-9577-be6ec66c02e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982843736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.982843736
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1408308080
Short name T568
Test name
Test status
Simulation time 47518454 ps
CPU time 0.71 seconds
Started Jun 09 01:36:30 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 194236 kb
Host smart-bd8d93c9-0ba8-49b4-8705-c78629bc8d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408308080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1408308080
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.4263606969
Short name T600
Test name
Test status
Simulation time 1582017353 ps
CPU time 21.53 seconds
Started Jun 09 01:36:34 PM PDT 24
Finished Jun 09 01:36:57 PM PDT 24
Peak memory 195576 kb
Host smart-69b54d49-2581-4067-bff7-7553a1e5382f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263606969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.4263606969
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2468910564
Short name T159
Test name
Test status
Simulation time 48616043 ps
CPU time 0.64 seconds
Started Jun 09 01:36:33 PM PDT 24
Finished Jun 09 01:36:34 PM PDT 24
Peak memory 194704 kb
Host smart-32584257-0b2d-4496-93ed-772797cc139d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468910564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2468910564
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3126736563
Short name T485
Test name
Test status
Simulation time 277471023 ps
CPU time 1.24 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:42 PM PDT 24
Peak memory 196712 kb
Host smart-93cf1f0a-8ce4-494d-b603-8ecb8d131252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126736563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3126736563
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2860249532
Short name T676
Test name
Test status
Simulation time 78294592 ps
CPU time 0.97 seconds
Started Jun 09 01:36:35 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 197072 kb
Host smart-2bc2503e-6ad8-4ad3-8d6d-31a35521fef3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860249532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2860249532
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2971040773
Short name T612
Test name
Test status
Simulation time 259148719 ps
CPU time 2.67 seconds
Started Jun 09 01:36:33 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 196940 kb
Host smart-6572d214-bb5f-4f3e-b4fc-0f8428b64fcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971040773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2971040773
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.510632986
Short name T275
Test name
Test status
Simulation time 252810312 ps
CPU time 1.21 seconds
Started Jun 09 01:36:29 PM PDT 24
Finished Jun 09 01:36:31 PM PDT 24
Peak memory 196940 kb
Host smart-903689e1-04ca-47f7-97fc-f8120850e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510632986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.510632986
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2205999076
Short name T301
Test name
Test status
Simulation time 64334029 ps
CPU time 1.2 seconds
Started Jun 09 01:36:28 PM PDT 24
Finished Jun 09 01:36:29 PM PDT 24
Peak memory 196644 kb
Host smart-a8bdd7b9-ba37-4788-a170-ea70a0aab430
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205999076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2205999076
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3420584907
Short name T361
Test name
Test status
Simulation time 541166969 ps
CPU time 3.54 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:44 PM PDT 24
Peak memory 198028 kb
Host smart-d81f2484-a22a-4e75-9dfb-f9f8032baf54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420584907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3420584907
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2614014780
Short name T622
Test name
Test status
Simulation time 46824806 ps
CPU time 1.24 seconds
Started Jun 09 01:36:27 PM PDT 24
Finished Jun 09 01:36:28 PM PDT 24
Peak memory 196856 kb
Host smart-26aef60b-c090-4a75-a55e-773cf2c41422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614014780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2614014780
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1237185321
Short name T537
Test name
Test status
Simulation time 47628418 ps
CPU time 1.26 seconds
Started Jun 09 01:36:29 PM PDT 24
Finished Jun 09 01:36:30 PM PDT 24
Peak memory 196348 kb
Host smart-594015ec-40bb-425e-afd8-9d1d754d7a3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237185321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1237185321
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4096459304
Short name T2
Test name
Test status
Simulation time 9075183054 ps
CPU time 98.16 seconds
Started Jun 09 01:36:33 PM PDT 24
Finished Jun 09 01:38:11 PM PDT 24
Peak memory 198300 kb
Host smart-47a057fc-ffc2-4e44-8fa7-501c79ab7808
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096459304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4096459304
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.207787911
Short name T55
Test name
Test status
Simulation time 44940733287 ps
CPU time 1324.33 seconds
Started Jun 09 01:36:35 PM PDT 24
Finished Jun 09 01:58:40 PM PDT 24
Peak memory 198192 kb
Host smart-e82a73d5-ada9-42a6-b791-6fdfe9564c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=207787911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.207787911
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1389646435
Short name T633
Test name
Test status
Simulation time 15254583 ps
CPU time 0.58 seconds
Started Jun 09 01:36:41 PM PDT 24
Finished Jun 09 01:36:42 PM PDT 24
Peak memory 193920 kb
Host smart-47505e4e-9119-4b05-ad03-20763afd52d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389646435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1389646435
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1017935339
Short name T630
Test name
Test status
Simulation time 44446461 ps
CPU time 1.01 seconds
Started Jun 09 01:36:36 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 195856 kb
Host smart-5a8faf5c-b060-42b6-ac0b-343de062e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017935339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1017935339
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2332756680
Short name T332
Test name
Test status
Simulation time 125784347 ps
CPU time 4.59 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:44 PM PDT 24
Peak memory 196420 kb
Host smart-33bba2c8-7631-4a2c-9b03-8c2d3b8c2ca1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332756680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2332756680
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3561208054
Short name T604
Test name
Test status
Simulation time 39527390 ps
CPU time 0.78 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 195804 kb
Host smart-b5a4cec8-e4b7-42d7-94c0-64451618af09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561208054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3561208054
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2957335347
Short name T519
Test name
Test status
Simulation time 37614057 ps
CPU time 0.85 seconds
Started Jun 09 01:36:35 PM PDT 24
Finished Jun 09 01:36:36 PM PDT 24
Peak memory 195528 kb
Host smart-6bf8c19c-63dd-4b22-9b24-dfe497fcb66d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957335347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2957335347
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2820270461
Short name T668
Test name
Test status
Simulation time 334833706 ps
CPU time 3.2 seconds
Started Jun 09 01:36:34 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 198148 kb
Host smart-29db832e-221b-473e-b670-d591c366f76d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820270461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2820270461
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3767365842
Short name T274
Test name
Test status
Simulation time 525492991 ps
CPU time 2.41 seconds
Started Jun 09 01:36:34 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 197140 kb
Host smart-6961cd78-14b4-441f-956f-f347d4c2ee6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767365842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3767365842
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1110060455
Short name T117
Test name
Test status
Simulation time 83766158 ps
CPU time 1.1 seconds
Started Jun 09 01:36:33 PM PDT 24
Finished Jun 09 01:36:34 PM PDT 24
Peak memory 195936 kb
Host smart-57c38f4c-4118-46a2-9a61-88cfc1f5ac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110060455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1110060455
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1527697032
Short name T220
Test name
Test status
Simulation time 67839312 ps
CPU time 0.76 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 195596 kb
Host smart-12379089-331d-456b-a594-4e6fe76eea4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527697032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1527697032
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1235682900
Short name T424
Test name
Test status
Simulation time 440959495 ps
CPU time 5.77 seconds
Started Jun 09 01:36:42 PM PDT 24
Finished Jun 09 01:36:48 PM PDT 24
Peak memory 197980 kb
Host smart-3fcf9b96-edcf-4398-82e8-37ad2066d299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235682900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1235682900
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1937266345
Short name T166
Test name
Test status
Simulation time 133676549 ps
CPU time 0.83 seconds
Started Jun 09 01:36:34 PM PDT 24
Finished Jun 09 01:36:36 PM PDT 24
Peak memory 195984 kb
Host smart-6071ef5b-b793-45b0-a01f-4bd262be473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937266345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1937266345
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3107289545
Short name T137
Test name
Test status
Simulation time 36867713 ps
CPU time 1.09 seconds
Started Jun 09 01:36:36 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 195560 kb
Host smart-d979f9c3-cc9a-41f4-92e5-ed973d01a5e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107289545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3107289545
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2366288152
Short name T128
Test name
Test status
Simulation time 68992969128 ps
CPU time 225.7 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:40:26 PM PDT 24
Peak memory 198220 kb
Host smart-87f50a7d-40c2-4252-b437-bd539a3ba6fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366288152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2366288152
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2434911357
Short name T647
Test name
Test status
Simulation time 18799475 ps
CPU time 0.57 seconds
Started Jun 09 01:36:38 PM PDT 24
Finished Jun 09 01:36:39 PM PDT 24
Peak memory 193944 kb
Host smart-962e15d6-8e5a-447e-a4ad-5824e021adbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434911357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2434911357
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.921825216
Short name T65
Test name
Test status
Simulation time 52430860 ps
CPU time 0.65 seconds
Started Jun 09 01:36:42 PM PDT 24
Finished Jun 09 01:36:43 PM PDT 24
Peak memory 194812 kb
Host smart-f042a3dd-b41d-4552-9b90-4ca1049c9caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921825216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.921825216
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3056262842
Short name T288
Test name
Test status
Simulation time 239648375 ps
CPU time 6.99 seconds
Started Jun 09 01:36:38 PM PDT 24
Finished Jun 09 01:36:45 PM PDT 24
Peak memory 197028 kb
Host smart-e5f37697-0d85-466e-aea5-74e8974bca58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056262842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3056262842
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.17481114
Short name T146
Test name
Test status
Simulation time 264867603 ps
CPU time 0.71 seconds
Started Jun 09 01:36:42 PM PDT 24
Finished Jun 09 01:36:43 PM PDT 24
Peak memory 195476 kb
Host smart-d7a65c93-d0e6-46b3-814e-4b474f45d232
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17481114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.17481114
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1426516583
Short name T329
Test name
Test status
Simulation time 157590356 ps
CPU time 1.45 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 197136 kb
Host smart-afbf77dc-28d2-4e5d-b7a6-b7b6126e23bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426516583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1426516583
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3992604815
Short name T523
Test name
Test status
Simulation time 149610007 ps
CPU time 1.63 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 198080 kb
Host smart-f043e8a5-4bd8-447f-ac7c-fe5af78133be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992604815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3992604815
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.716962862
Short name T341
Test name
Test status
Simulation time 219361126 ps
CPU time 1.38 seconds
Started Jun 09 01:36:42 PM PDT 24
Finished Jun 09 01:36:43 PM PDT 24
Peak memory 196948 kb
Host smart-66711049-d11d-4803-9a61-11d9a1cc5084
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716962862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
716962862
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.490178650
Short name T366
Test name
Test status
Simulation time 177630292 ps
CPU time 1.17 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:42 PM PDT 24
Peak memory 195848 kb
Host smart-9328d237-6d79-4591-9c15-f0ee56403222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490178650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.490178650
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1109382251
Short name T508
Test name
Test status
Simulation time 20508490 ps
CPU time 0.76 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:46 PM PDT 24
Peak memory 195504 kb
Host smart-2b2208e4-6c76-4a6c-aff5-64a744ae9fbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109382251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1109382251
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3438712515
Short name T614
Test name
Test status
Simulation time 72883446 ps
CPU time 1.29 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 198000 kb
Host smart-e312cac4-ba1d-49c0-b4a0-4b75546b54e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438712515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3438712515
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.152250629
Short name T413
Test name
Test status
Simulation time 51082764 ps
CPU time 1.09 seconds
Started Jun 09 01:36:39 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 196324 kb
Host smart-e79eae82-e3c2-4923-aaf7-4ef9bdbe333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152250629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.152250629
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.406122310
Short name T625
Test name
Test status
Simulation time 72321088 ps
CPU time 1.09 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:41 PM PDT 24
Peak memory 195696 kb
Host smart-a09daa03-2ffc-4f24-8ab3-b7c15692fdb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406122310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.406122310
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3579884022
Short name T525
Test name
Test status
Simulation time 3159636541 ps
CPU time 74.41 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:37:55 PM PDT 24
Peak memory 198144 kb
Host smart-e3b905d4-19dd-471b-bd02-0d6e247e2a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579884022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3579884022
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.618025590
Short name T459
Test name
Test status
Simulation time 165086391961 ps
CPU time 714.47 seconds
Started Jun 09 01:36:41 PM PDT 24
Finished Jun 09 01:48:36 PM PDT 24
Peak memory 198292 kb
Host smart-50ad8257-75bf-43fd-8f74-52c05024fde2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=618025590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.618025590
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1562916913
Short name T558
Test name
Test status
Simulation time 46944375 ps
CPU time 0.57 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:46 PM PDT 24
Peak memory 194148 kb
Host smart-9fa306c8-dfa6-4bb0-b6d1-7e88ac02634a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562916913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1562916913
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3772686102
Short name T683
Test name
Test status
Simulation time 47403122 ps
CPU time 0.69 seconds
Started Jun 09 01:36:42 PM PDT 24
Finished Jun 09 01:36:43 PM PDT 24
Peak memory 194212 kb
Host smart-691196f1-dbbb-4794-b8af-545ebd6c903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772686102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3772686102
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3390624108
Short name T141
Test name
Test status
Simulation time 802763618 ps
CPU time 26.94 seconds
Started Jun 09 01:36:41 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 196944 kb
Host smart-7ad45ea1-0867-42be-a583-8f26c8ed3f75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390624108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3390624108
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3449573870
Short name T21
Test name
Test status
Simulation time 158736494 ps
CPU time 0.74 seconds
Started Jun 09 01:36:44 PM PDT 24
Finished Jun 09 01:36:45 PM PDT 24
Peak memory 194936 kb
Host smart-89712399-3065-4f72-8b5b-e031d5f96d37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449573870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3449573870
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.904091907
Short name T231
Test name
Test status
Simulation time 452082161 ps
CPU time 1.49 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:47 PM PDT 24
Peak memory 198088 kb
Host smart-591b5e72-011e-405b-85e9-c478c055530a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904091907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.904091907
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3293023009
Short name T197
Test name
Test status
Simulation time 95425993 ps
CPU time 2.97 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:43 PM PDT 24
Peak memory 198012 kb
Host smart-3e4dfd90-7bb2-4ab2-8e5e-de0c0c11fe3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293023009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3293023009
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2913346934
Short name T161
Test name
Test status
Simulation time 46614938 ps
CPU time 1.3 seconds
Started Jun 09 01:36:38 PM PDT 24
Finished Jun 09 01:36:40 PM PDT 24
Peak memory 196540 kb
Host smart-fbb0f57f-6eaa-462f-ad76-bd2ce018bb38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913346934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2913346934
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3729430571
Short name T394
Test name
Test status
Simulation time 108214299 ps
CPU time 1.15 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:42 PM PDT 24
Peak memory 196812 kb
Host smart-045f66f2-7a11-4c80-bed3-9644ff5d8843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729430571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3729430571
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.410201887
Short name T219
Test name
Test status
Simulation time 93877310 ps
CPU time 1.07 seconds
Started Jun 09 01:36:42 PM PDT 24
Finished Jun 09 01:36:43 PM PDT 24
Peak memory 196040 kb
Host smart-19308866-f693-4a10-ae5c-b3f6d0a29607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410201887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.410201887
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3686486428
Short name T267
Test name
Test status
Simulation time 90881930 ps
CPU time 4.22 seconds
Started Jun 09 01:36:46 PM PDT 24
Finished Jun 09 01:36:50 PM PDT 24
Peak memory 197944 kb
Host smart-9d0a7910-ec83-44ef-b419-620162f62467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686486428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3686486428
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1863394679
Short name T93
Test name
Test status
Simulation time 65915099 ps
CPU time 1.35 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:42 PM PDT 24
Peak memory 197132 kb
Host smart-6ac0fa4c-931a-492c-b105-fd17690853b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863394679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1863394679
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.973234832
Short name T465
Test name
Test status
Simulation time 156671908 ps
CPU time 1 seconds
Started Jun 09 01:36:40 PM PDT 24
Finished Jun 09 01:36:42 PM PDT 24
Peak memory 195788 kb
Host smart-3e65ee28-3099-438c-9bb2-5796907e407f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973234832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.973234832
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4123813712
Short name T407
Test name
Test status
Simulation time 9646709858 ps
CPU time 132.89 seconds
Started Jun 09 01:36:46 PM PDT 24
Finished Jun 09 01:39:00 PM PDT 24
Peak memory 198228 kb
Host smart-2d49b840-4ffa-419d-af82-10777ea5e0a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123813712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4123813712
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2552677670
Short name T227
Test name
Test status
Simulation time 11152992 ps
CPU time 0.55 seconds
Started Jun 09 01:34:27 PM PDT 24
Finished Jun 09 01:34:28 PM PDT 24
Peak memory 193956 kb
Host smart-5760d535-8ed3-4040-ad76-520b2dc69ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552677670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2552677670
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2553553467
Short name T491
Test name
Test status
Simulation time 64487883 ps
CPU time 0.72 seconds
Started Jun 09 01:34:27 PM PDT 24
Finished Jun 09 01:34:28 PM PDT 24
Peak memory 194232 kb
Host smart-69add7f0-88c3-4968-a7b3-fd1e3ff2e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553553467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2553553467
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4040824886
Short name T213
Test name
Test status
Simulation time 568299343 ps
CPU time 7.25 seconds
Started Jun 09 01:34:28 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 198028 kb
Host smart-3a07384e-980a-468e-89e3-1bf47685f034
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040824886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4040824886
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.327531610
Short name T53
Test name
Test status
Simulation time 256440538 ps
CPU time 0.88 seconds
Started Jun 09 01:34:27 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 197292 kb
Host smart-4774b0bf-b22f-43ad-99b2-10b9de0f7079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327531610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.327531610
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1611769542
Short name T152
Test name
Test status
Simulation time 276952312 ps
CPU time 1.24 seconds
Started Jun 09 01:34:28 PM PDT 24
Finished Jun 09 01:34:30 PM PDT 24
Peak memory 195848 kb
Host smart-04e37eb5-f204-49bc-8c2b-0a4ebe7d038f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611769542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1611769542
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.800153912
Short name T705
Test name
Test status
Simulation time 82924108 ps
CPU time 1.06 seconds
Started Jun 09 01:34:25 PM PDT 24
Finished Jun 09 01:34:27 PM PDT 24
Peak memory 196288 kb
Host smart-04b16bf0-fa35-4636-9f7b-5a8afbbd5938
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800153912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.800153912
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2034000787
Short name T627
Test name
Test status
Simulation time 33782901 ps
CPU time 0.91 seconds
Started Jun 09 01:34:29 PM PDT 24
Finished Jun 09 01:34:30 PM PDT 24
Peak memory 195664 kb
Host smart-d2205156-eb7e-41b7-baf4-5ca9c822bfbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034000787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2034000787
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1710990207
Short name T376
Test name
Test status
Simulation time 49995102 ps
CPU time 1.11 seconds
Started Jun 09 01:34:28 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 196108 kb
Host smart-71b9ab9b-3f27-4350-aa2a-65e5ce8f4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710990207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1710990207
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1540076879
Short name T458
Test name
Test status
Simulation time 38156295 ps
CPU time 0.69 seconds
Started Jun 09 01:34:26 PM PDT 24
Finished Jun 09 01:34:27 PM PDT 24
Peak memory 194344 kb
Host smart-ad59d42a-2e0f-440c-8aec-eadd2324e715
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540076879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1540076879
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.959139261
Short name T318
Test name
Test status
Simulation time 98697073 ps
CPU time 2.39 seconds
Started Jun 09 01:34:33 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 197992 kb
Host smart-3e1a6237-ad56-4ede-b45e-e7847f5cb2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959139261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.959139261
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.639163408
Short name T47
Test name
Test status
Simulation time 86351170 ps
CPU time 0.98 seconds
Started Jun 09 01:34:27 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 215024 kb
Host smart-57fc83b3-e78e-4f5f-a9ba-73586e963a5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639163408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.639163408
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.933774924
Short name T23
Test name
Test status
Simulation time 45014168 ps
CPU time 0.93 seconds
Started Jun 09 01:34:27 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 195552 kb
Host smart-156872e5-4db9-4be4-8838-53c2687cdf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933774924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.933774924
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.587433436
Short name T158
Test name
Test status
Simulation time 773851947 ps
CPU time 1.12 seconds
Started Jun 09 01:34:41 PM PDT 24
Finished Jun 09 01:34:42 PM PDT 24
Peak memory 195844 kb
Host smart-5b922e2b-1977-4d0f-9a76-272d9a63ff9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587433436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.587433436
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1157973685
Short name T322
Test name
Test status
Simulation time 5719804552 ps
CPU time 153.53 seconds
Started Jun 09 01:34:27 PM PDT 24
Finished Jun 09 01:37:01 PM PDT 24
Peak memory 198236 kb
Host smart-6e5f7eaa-1040-432a-a364-6f1f3f15bb53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157973685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1157973685
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1035813224
Short name T599
Test name
Test status
Simulation time 35290202 ps
CPU time 0.57 seconds
Started Jun 09 01:36:49 PM PDT 24
Finished Jun 09 01:36:49 PM PDT 24
Peak memory 193960 kb
Host smart-c369aa40-d078-4251-b4a8-0d2d2b779315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035813224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1035813224
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3297135016
Short name T294
Test name
Test status
Simulation time 28035829 ps
CPU time 0.82 seconds
Started Jun 09 01:36:46 PM PDT 24
Finished Jun 09 01:36:47 PM PDT 24
Peak memory 197104 kb
Host smart-a7b56332-07dc-43e7-aea9-391ec63f07cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297135016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3297135016
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3272544290
Short name T694
Test name
Test status
Simulation time 1213401137 ps
CPU time 9.41 seconds
Started Jun 09 01:36:44 PM PDT 24
Finished Jun 09 01:36:54 PM PDT 24
Peak memory 196820 kb
Host smart-bddff7b2-2826-4e53-a9a0-bb229e1a6242
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272544290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3272544290
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4232718436
Short name T330
Test name
Test status
Simulation time 84754543 ps
CPU time 0.73 seconds
Started Jun 09 01:36:46 PM PDT 24
Finished Jun 09 01:36:47 PM PDT 24
Peak memory 195988 kb
Host smart-5710fd20-bc00-4f71-b4b9-70fb2598d1eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232718436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4232718436
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.93288014
Short name T528
Test name
Test status
Simulation time 82012269 ps
CPU time 0.74 seconds
Started Jun 09 01:36:44 PM PDT 24
Finished Jun 09 01:36:46 PM PDT 24
Peak memory 195528 kb
Host smart-7b2706fc-bf56-4cf9-9857-bf84c1cfbb14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93288014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.93288014
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3463264316
Short name T594
Test name
Test status
Simulation time 90630060 ps
CPU time 3.81 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:49 PM PDT 24
Peak memory 198144 kb
Host smart-600191ee-69f4-4399-943e-edf130a4e933
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463264316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3463264316
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1551292129
Short name T200
Test name
Test status
Simulation time 45677034 ps
CPU time 1.48 seconds
Started Jun 09 01:36:44 PM PDT 24
Finished Jun 09 01:36:46 PM PDT 24
Peak memory 195832 kb
Host smart-3bd6be0a-5220-4c6b-bb0e-c60684926de2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551292129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1551292129
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1773510547
Short name T222
Test name
Test status
Simulation time 129557009 ps
CPU time 0.82 seconds
Started Jun 09 01:36:44 PM PDT 24
Finished Jun 09 01:36:45 PM PDT 24
Peak memory 195460 kb
Host smart-4ebc720a-9d5a-49a9-bc7d-63971e190842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773510547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1773510547
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3560610167
Short name T602
Test name
Test status
Simulation time 23698072 ps
CPU time 0.88 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:47 PM PDT 24
Peak memory 196684 kb
Host smart-1caa79d3-7bc7-47fd-bbfc-add76f143479
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560610167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3560610167
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3431330873
Short name T8
Test name
Test status
Simulation time 1595715485 ps
CPU time 3.58 seconds
Started Jun 09 01:36:46 PM PDT 24
Finished Jun 09 01:36:50 PM PDT 24
Peak memory 197980 kb
Host smart-130f051a-71fa-43fe-ac1c-923c134f4e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431330873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3431330873
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2092786531
Short name T268
Test name
Test status
Simulation time 204302357 ps
CPU time 0.94 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:47 PM PDT 24
Peak memory 196516 kb
Host smart-3bb21e65-d90c-4bae-bb87-41991fc75511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092786531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2092786531
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1059934875
Short name T162
Test name
Test status
Simulation time 63784682 ps
CPU time 1.26 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:36:46 PM PDT 24
Peak memory 196952 kb
Host smart-fa4f15c6-14a7-4e0e-965d-c1e635b2e1d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059934875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1059934875
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1468790421
Short name T628
Test name
Test status
Simulation time 26932921662 ps
CPU time 166.64 seconds
Started Jun 09 01:36:45 PM PDT 24
Finished Jun 09 01:39:32 PM PDT 24
Peak memory 198220 kb
Host smart-e3ef8db3-7f03-41b0-ad6a-61aa69827baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468790421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1468790421
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2089892788
Short name T290
Test name
Test status
Simulation time 21483444 ps
CPU time 0.59 seconds
Started Jun 09 01:36:49 PM PDT 24
Finished Jun 09 01:36:50 PM PDT 24
Peak memory 193936 kb
Host smart-5edc1afd-dc7b-45ff-beb3-5fb6332c36a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089892788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2089892788
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3526069201
Short name T576
Test name
Test status
Simulation time 35861433 ps
CPU time 0.82 seconds
Started Jun 09 01:36:56 PM PDT 24
Finished Jun 09 01:36:57 PM PDT 24
Peak memory 195468 kb
Host smart-4ab97f8a-268a-4b19-80c4-64dda186053b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526069201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3526069201
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2646376132
Short name T581
Test name
Test status
Simulation time 624835568 ps
CPU time 18.49 seconds
Started Jun 09 01:36:53 PM PDT 24
Finished Jun 09 01:37:11 PM PDT 24
Peak memory 197204 kb
Host smart-b8ee2998-d47c-4956-ba56-e0982a79cb13
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646376132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2646376132
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2758499551
Short name T313
Test name
Test status
Simulation time 330220119 ps
CPU time 1 seconds
Started Jun 09 01:36:52 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 197376 kb
Host smart-60755802-9452-406d-a729-7abb067937f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758499551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2758499551
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2581230334
Short name T127
Test name
Test status
Simulation time 42844139 ps
CPU time 0.85 seconds
Started Jun 09 01:36:52 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 195640 kb
Host smart-25f6a6f1-b4e9-421a-9357-5add274ce3b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581230334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2581230334
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3370396404
Short name T238
Test name
Test status
Simulation time 221335198 ps
CPU time 1.18 seconds
Started Jun 09 01:36:52 PM PDT 24
Finished Jun 09 01:36:54 PM PDT 24
Peak memory 196348 kb
Host smart-c11c8552-0334-4bd4-a2cd-96fb056d908a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370396404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3370396404
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2144089852
Short name T442
Test name
Test status
Simulation time 60700622 ps
CPU time 1.8 seconds
Started Jun 09 01:36:50 PM PDT 24
Finished Jun 09 01:36:52 PM PDT 24
Peak memory 196212 kb
Host smart-6ce98e4c-6c4d-43f6-b42b-57ddd498addd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144089852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2144089852
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1259936405
Short name T185
Test name
Test status
Simulation time 24105182 ps
CPU time 0.77 seconds
Started Jun 09 01:36:50 PM PDT 24
Finished Jun 09 01:36:51 PM PDT 24
Peak memory 195716 kb
Host smart-f0464b18-d5cd-44c6-a791-120686adc7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259936405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1259936405
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1279429601
Short name T536
Test name
Test status
Simulation time 56373435 ps
CPU time 1.32 seconds
Started Jun 09 01:36:53 PM PDT 24
Finished Jun 09 01:36:55 PM PDT 24
Peak memory 196900 kb
Host smart-a6f801be-7555-4d36-ac23-4c2405c5acea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279429601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1279429601
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1284332521
Short name T123
Test name
Test status
Simulation time 63148130 ps
CPU time 3.03 seconds
Started Jun 09 01:36:51 PM PDT 24
Finished Jun 09 01:36:54 PM PDT 24
Peak memory 198008 kb
Host smart-a10eff1d-c85d-449b-a002-a27cdafa6f22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284332521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1284332521
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1620985539
Short name T171
Test name
Test status
Simulation time 155754486 ps
CPU time 1.23 seconds
Started Jun 09 01:36:51 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 196784 kb
Host smart-5028bae9-dfad-4c7e-9874-e9eecbc699fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620985539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1620985539
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.640953145
Short name T606
Test name
Test status
Simulation time 278460447 ps
CPU time 1.31 seconds
Started Jun 09 01:36:53 PM PDT 24
Finished Jun 09 01:36:54 PM PDT 24
Peak memory 195564 kb
Host smart-e8975c2f-cd21-4c3e-95db-8958bc98c3c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640953145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.640953145
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3108072144
Short name T585
Test name
Test status
Simulation time 7303733314 ps
CPU time 198.97 seconds
Started Jun 09 01:36:53 PM PDT 24
Finished Jun 09 01:40:12 PM PDT 24
Peak memory 198236 kb
Host smart-0623ae95-723f-4380-aa45-07d33f8e0990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108072144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3108072144
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4097519113
Short name T60
Test name
Test status
Simulation time 35643598755 ps
CPU time 435.74 seconds
Started Jun 09 01:36:51 PM PDT 24
Finished Jun 09 01:44:07 PM PDT 24
Peak memory 198248 kb
Host smart-65c7930c-3c00-4e57-b27b-827ae98f6ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4097519113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4097519113
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2264360162
Short name T653
Test name
Test status
Simulation time 13262686 ps
CPU time 0.57 seconds
Started Jun 09 01:36:55 PM PDT 24
Finished Jun 09 01:36:56 PM PDT 24
Peak memory 193896 kb
Host smart-8c4057f4-400d-4a1f-b1a5-7db78d42f245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264360162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2264360162
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3692166375
Short name T513
Test name
Test status
Simulation time 158583746 ps
CPU time 0.74 seconds
Started Jun 09 01:36:52 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 195408 kb
Host smart-dd33dc17-e83b-4b82-a01d-1d4cc504384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692166375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3692166375
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3322477524
Short name T190
Test name
Test status
Simulation time 228314196 ps
CPU time 4.07 seconds
Started Jun 09 01:36:55 PM PDT 24
Finished Jun 09 01:37:00 PM PDT 24
Peak memory 196568 kb
Host smart-99512fda-2811-4536-9537-57466934e2f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322477524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3322477524
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.379273281
Short name T251
Test name
Test status
Simulation time 172592079 ps
CPU time 1.07 seconds
Started Jun 09 01:36:56 PM PDT 24
Finished Jun 09 01:36:58 PM PDT 24
Peak memory 196640 kb
Host smart-45163421-194b-4e63-9169-75f6e12e3245
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379273281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.379273281
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2691137148
Short name T196
Test name
Test status
Simulation time 553394755 ps
CPU time 0.83 seconds
Started Jun 09 01:36:50 PM PDT 24
Finished Jun 09 01:36:52 PM PDT 24
Peak memory 196408 kb
Host smart-6a016d11-e885-452d-8774-b7040d52dde4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691137148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2691137148
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1528332257
Short name T690
Test name
Test status
Simulation time 256948894 ps
CPU time 2.99 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:37:00 PM PDT 24
Peak memory 198100 kb
Host smart-e894c71c-4dac-4a06-82db-46aca79447df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528332257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1528332257
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3323453435
Short name T181
Test name
Test status
Simulation time 369470874 ps
CPU time 2.4 seconds
Started Jun 09 01:36:50 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 198080 kb
Host smart-5759dff7-e210-409e-9ea2-b5a8dbd89df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323453435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3323453435
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3784484479
Short name T121
Test name
Test status
Simulation time 46711285 ps
CPU time 0.97 seconds
Started Jun 09 01:36:52 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 195832 kb
Host smart-1811b699-d741-4130-aac2-e29e0327a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784484479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3784484479
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2608228878
Short name T279
Test name
Test status
Simulation time 190142380 ps
CPU time 1.21 seconds
Started Jun 09 01:36:51 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 196072 kb
Host smart-68fc68f8-cc2b-4872-9055-dcff9dce0d70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608228878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2608228878
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3983327912
Short name T626
Test name
Test status
Simulation time 226005102 ps
CPU time 4.99 seconds
Started Jun 09 01:36:55 PM PDT 24
Finished Jun 09 01:37:01 PM PDT 24
Peak memory 198008 kb
Host smart-2f66a1a9-2d52-486d-ae8e-a7c92c25ce67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983327912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3983327912
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2098643617
Short name T168
Test name
Test status
Simulation time 38756900 ps
CPU time 0.85 seconds
Started Jun 09 01:36:51 PM PDT 24
Finished Jun 09 01:36:52 PM PDT 24
Peak memory 195392 kb
Host smart-ec64e8b4-6746-46c6-bdf9-d2eef394fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098643617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2098643617
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2010285864
Short name T477
Test name
Test status
Simulation time 362208628 ps
CPU time 0.98 seconds
Started Jun 09 01:36:52 PM PDT 24
Finished Jun 09 01:36:53 PM PDT 24
Peak memory 195564 kb
Host smart-88ba427a-6162-475c-ad15-b20a5323c881
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010285864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2010285864
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.314012923
Short name T401
Test name
Test status
Simulation time 65537218580 ps
CPU time 169.43 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:39:47 PM PDT 24
Peak memory 198136 kb
Host smart-d0b629b8-ed01-4e76-a275-bb824c1faeed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314012923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.314012923
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3165918519
Short name T342
Test name
Test status
Simulation time 10611221 ps
CPU time 0.56 seconds
Started Jun 09 01:37:02 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 193540 kb
Host smart-3d355d25-7649-4f2f-b6db-4268f913428d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165918519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3165918519
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3701326010
Short name T500
Test name
Test status
Simulation time 107063590 ps
CPU time 0.79 seconds
Started Jun 09 01:37:02 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 196092 kb
Host smart-8b38173a-88c3-4185-811f-3081bcaf547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701326010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3701326010
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3134406401
Short name T270
Test name
Test status
Simulation time 151373770 ps
CPU time 5.58 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 196968 kb
Host smart-fbb62d32-5ed3-4b26-a626-11786671e182
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134406401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3134406401
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2880935336
Short name T249
Test name
Test status
Simulation time 43227269 ps
CPU time 0.82 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:36:58 PM PDT 24
Peak memory 195984 kb
Host smart-c47cf4cb-f344-40e5-9e8f-00eadc2ab28c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880935336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2880935336
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4249256139
Short name T480
Test name
Test status
Simulation time 47173739 ps
CPU time 1.35 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:36:58 PM PDT 24
Peak memory 197044 kb
Host smart-d93dfd7d-670c-42e3-aca6-de6f547e3a83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249256139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4249256139
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.338152596
Short name T584
Test name
Test status
Simulation time 58083840 ps
CPU time 2.18 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:37:00 PM PDT 24
Peak memory 198148 kb
Host smart-db0f97dc-3330-45fb-8fa7-de13c1cd53a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338152596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.338152596
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3751955672
Short name T487
Test name
Test status
Simulation time 49876132 ps
CPU time 1 seconds
Started Jun 09 01:36:55 PM PDT 24
Finished Jun 09 01:36:57 PM PDT 24
Peak memory 195852 kb
Host smart-bb2bf22f-682f-47bc-999f-ac94abbbc53a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751955672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3751955672
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4072238083
Short name T383
Test name
Test status
Simulation time 67507863 ps
CPU time 1.23 seconds
Started Jun 09 01:36:56 PM PDT 24
Finished Jun 09 01:36:58 PM PDT 24
Peak memory 197104 kb
Host smart-59f9cc50-241c-4733-94c5-59362626ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072238083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4072238083
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1581521456
Short name T261
Test name
Test status
Simulation time 76094264 ps
CPU time 0.73 seconds
Started Jun 09 01:36:54 PM PDT 24
Finished Jun 09 01:36:55 PM PDT 24
Peak memory 195448 kb
Host smart-4bff6041-772b-4650-8278-005ed38e27fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581521456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1581521456
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.681438046
Short name T662
Test name
Test status
Simulation time 82105199 ps
CPU time 1.17 seconds
Started Jun 09 01:36:54 PM PDT 24
Finished Jun 09 01:36:56 PM PDT 24
Peak memory 197944 kb
Host smart-ab16edda-ad00-48d4-8929-f8351abc9a66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681438046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.681438046
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4015701869
Short name T125
Test name
Test status
Simulation time 78694626 ps
CPU time 1.51 seconds
Started Jun 09 01:36:55 PM PDT 24
Finished Jun 09 01:36:57 PM PDT 24
Peak memory 196248 kb
Host smart-39d5a9f7-4913-42f2-ad06-51daa90f071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015701869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4015701869
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2145209824
Short name T339
Test name
Test status
Simulation time 24904170 ps
CPU time 0.94 seconds
Started Jun 09 01:36:55 PM PDT 24
Finished Jun 09 01:36:57 PM PDT 24
Peak memory 195832 kb
Host smart-6d57f638-0228-4daa-bd4b-ef9195b9bc38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145209824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2145209824
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1423107186
Short name T571
Test name
Test status
Simulation time 46275395086 ps
CPU time 164.59 seconds
Started Jun 09 01:36:57 PM PDT 24
Finished Jun 09 01:39:42 PM PDT 24
Peak memory 198276 kb
Host smart-a449a4a4-3b6d-4467-ac75-917fc99cb0a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423107186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1423107186
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3789152334
Short name T61
Test name
Test status
Simulation time 594593216706 ps
CPU time 1985.04 seconds
Started Jun 09 01:36:56 PM PDT 24
Finished Jun 09 02:10:01 PM PDT 24
Peak memory 198256 kb
Host smart-51cf7b56-cb6b-456a-af92-cbe2a34ff5f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3789152334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3789152334
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1572348109
Short name T610
Test name
Test status
Simulation time 15897667 ps
CPU time 0.6 seconds
Started Jun 09 01:37:02 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 194148 kb
Host smart-3b817cf7-83fb-45ca-bc4b-ec90cba216b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572348109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1572348109
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3773613225
Short name T596
Test name
Test status
Simulation time 53710489 ps
CPU time 0.69 seconds
Started Jun 09 01:36:59 PM PDT 24
Finished Jun 09 01:37:00 PM PDT 24
Peak memory 194248 kb
Host smart-0afd8897-57e9-4f2f-9002-a9c6864109eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773613225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3773613225
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1764410121
Short name T639
Test name
Test status
Simulation time 577973040 ps
CPU time 17.5 seconds
Started Jun 09 01:36:59 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 195568 kb
Host smart-33f83f3d-d610-460b-843f-1477d0a3f983
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764410121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1764410121
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2462938930
Short name T586
Test name
Test status
Simulation time 369405608 ps
CPU time 1.09 seconds
Started Jun 09 01:37:02 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 197892 kb
Host smart-fd49d57a-d1e7-458e-b5da-dd2fb5eb131f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462938930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2462938930
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2868340766
Short name T463
Test name
Test status
Simulation time 267978261 ps
CPU time 1.12 seconds
Started Jun 09 01:37:01 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 195960 kb
Host smart-99f66bbc-459b-4c34-8a8f-123e66ee33e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868340766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2868340766
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.423693097
Short name T566
Test name
Test status
Simulation time 311566794 ps
CPU time 3.38 seconds
Started Jun 09 01:37:03 PM PDT 24
Finished Jun 09 01:37:06 PM PDT 24
Peak memory 198148 kb
Host smart-31109190-b1c3-4663-a075-a7277be76b63
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423693097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.423693097
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2622810510
Short name T214
Test name
Test status
Simulation time 199101809 ps
CPU time 1.83 seconds
Started Jun 09 01:37:02 PM PDT 24
Finished Jun 09 01:37:04 PM PDT 24
Peak memory 196728 kb
Host smart-39cbf2c1-9905-41a8-aab1-e745a119b0a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622810510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2622810510
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4077155202
Short name T714
Test name
Test status
Simulation time 48459975 ps
CPU time 1.08 seconds
Started Jun 09 01:37:02 PM PDT 24
Finished Jun 09 01:37:04 PM PDT 24
Peak memory 196032 kb
Host smart-5bdf4ee3-e3ba-4536-8be7-961f432e244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077155202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4077155202
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2696865589
Short name T292
Test name
Test status
Simulation time 118615106 ps
CPU time 0.97 seconds
Started Jun 09 01:37:01 PM PDT 24
Finished Jun 09 01:37:03 PM PDT 24
Peak memory 195900 kb
Host smart-bbb66d52-9690-468a-becc-80e6bff88c6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696865589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2696865589
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3266692923
Short name T504
Test name
Test status
Simulation time 71092557 ps
CPU time 1.92 seconds
Started Jun 09 01:37:03 PM PDT 24
Finished Jun 09 01:37:05 PM PDT 24
Peak memory 198084 kb
Host smart-325c9226-68b9-445f-af8f-16fdd058dd19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266692923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3266692923
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2736897727
Short name T236
Test name
Test status
Simulation time 103679385 ps
CPU time 1.43 seconds
Started Jun 09 01:37:00 PM PDT 24
Finished Jun 09 01:37:02 PM PDT 24
Peak memory 197936 kb
Host smart-74edb1ca-dc33-4396-8efb-c0ce32c8cefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736897727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2736897727
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.370331582
Short name T224
Test name
Test status
Simulation time 199488889 ps
CPU time 1.1 seconds
Started Jun 09 01:37:00 PM PDT 24
Finished Jun 09 01:37:01 PM PDT 24
Peak memory 195680 kb
Host smart-950c2a09-7986-4f60-b94d-3c582991763b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370331582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.370331582
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.782185851
Short name T189
Test name
Test status
Simulation time 7090187496 ps
CPU time 182.4 seconds
Started Jun 09 01:37:00 PM PDT 24
Finished Jun 09 01:40:02 PM PDT 24
Peak memory 198212 kb
Host smart-1e5b5839-d026-46ba-b42d-095072e5abbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782185851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.782185851
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2559762795
Short name T191
Test name
Test status
Simulation time 46722541 ps
CPU time 0.58 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 194196 kb
Host smart-fd177fbf-b246-448c-86fa-e9a9af460c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559762795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2559762795
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4292510651
Short name T207
Test name
Test status
Simulation time 61796736 ps
CPU time 0.72 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 195316 kb
Host smart-e455b076-eaaf-43fe-9436-0946d53e058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292510651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4292510651
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2953285759
Short name T441
Test name
Test status
Simulation time 955577192 ps
CPU time 23.2 seconds
Started Jun 09 01:37:08 PM PDT 24
Finished Jun 09 01:37:31 PM PDT 24
Peak memory 195528 kb
Host smart-a39a72e4-9174-4982-8356-56c8f0c88b37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953285759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2953285759
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3038265102
Short name T20
Test name
Test status
Simulation time 82837439 ps
CPU time 0.96 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 196724 kb
Host smart-94d9d54c-c94c-4528-845a-c2df7a490df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038265102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3038265102
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1227501623
Short name T12
Test name
Test status
Simulation time 911572988 ps
CPU time 1.39 seconds
Started Jun 09 01:37:06 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 198088 kb
Host smart-68517893-47ea-4600-8803-1a64fb1a3f24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227501623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1227501623
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.540087823
Short name T264
Test name
Test status
Simulation time 193325532 ps
CPU time 1.48 seconds
Started Jun 09 01:37:13 PM PDT 24
Finished Jun 09 01:37:15 PM PDT 24
Peak memory 196392 kb
Host smart-6da7a824-574d-4a4a-9b6c-c32907ace59e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540087823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.540087823
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4080859390
Short name T631
Test name
Test status
Simulation time 126754495 ps
CPU time 1.48 seconds
Started Jun 09 01:37:09 PM PDT 24
Finished Jun 09 01:37:11 PM PDT 24
Peak memory 196136 kb
Host smart-74f6598e-c579-4134-901f-6ca5b4300717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080859390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4080859390
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2376838411
Short name T346
Test name
Test status
Simulation time 77674727 ps
CPU time 1.05 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 196720 kb
Host smart-c77222cc-1822-4ea5-938b-f16b1f06670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376838411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2376838411
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.439758165
Short name T358
Test name
Test status
Simulation time 164556962 ps
CPU time 1.07 seconds
Started Jun 09 01:37:05 PM PDT 24
Finished Jun 09 01:37:06 PM PDT 24
Peak memory 196144 kb
Host smart-652bfd10-ddbf-413c-9ea9-fe9249ed4bb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439758165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.439758165
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4177085369
Short name T609
Test name
Test status
Simulation time 181454965 ps
CPU time 2.42 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:10 PM PDT 24
Peak memory 198056 kb
Host smart-168ae09b-9d13-4777-ba72-2cd490683b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177085369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4177085369
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3861912625
Short name T517
Test name
Test status
Simulation time 186189616 ps
CPU time 1.01 seconds
Started Jun 09 01:37:08 PM PDT 24
Finished Jun 09 01:37:09 PM PDT 24
Peak memory 195684 kb
Host smart-59c08629-5269-46a1-9a6b-a935362f344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861912625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3861912625
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2216084220
Short name T691
Test name
Test status
Simulation time 28207662 ps
CPU time 0.81 seconds
Started Jun 09 01:37:06 PM PDT 24
Finished Jun 09 01:37:07 PM PDT 24
Peak memory 195304 kb
Host smart-9de1ca6a-ef9c-4328-9e85-5c0fb29fff5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216084220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2216084220
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1042997758
Short name T654
Test name
Test status
Simulation time 1106817658 ps
CPU time 32.87 seconds
Started Jun 09 01:37:08 PM PDT 24
Finished Jun 09 01:37:41 PM PDT 24
Peak memory 198060 kb
Host smart-49c1cc2a-cfbc-40ba-afb0-9222c9e173b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042997758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1042997758
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3960032605
Short name T430
Test name
Test status
Simulation time 14765572 ps
CPU time 0.57 seconds
Started Jun 09 01:37:12 PM PDT 24
Finished Jun 09 01:37:13 PM PDT 24
Peak memory 193920 kb
Host smart-25660623-5084-4780-9787-3f8d9749a483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960032605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3960032605
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.748792243
Short name T616
Test name
Test status
Simulation time 45392079 ps
CPU time 0.66 seconds
Started Jun 09 01:37:06 PM PDT 24
Finished Jun 09 01:37:07 PM PDT 24
Peak memory 194044 kb
Host smart-d43212e3-4349-44e3-8053-b485191649a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748792243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.748792243
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4002159079
Short name T140
Test name
Test status
Simulation time 6069442949 ps
CPU time 16.2 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:27 PM PDT 24
Peak memory 196680 kb
Host smart-eaacd8b4-24dd-40c3-9fc9-487c564ebda0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002159079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4002159079
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2963649406
Short name T354
Test name
Test status
Simulation time 200813294 ps
CPU time 0.92 seconds
Started Jun 09 01:37:10 PM PDT 24
Finished Jun 09 01:37:12 PM PDT 24
Peak memory 197976 kb
Host smart-c4ac1fce-1965-4b6d-b402-3018790af171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963649406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2963649406
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4293714568
Short name T650
Test name
Test status
Simulation time 43382305 ps
CPU time 0.62 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 194232 kb
Host smart-96ddcd14-d4d2-4dda-a99b-24c6f8d4d50d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293714568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4293714568
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3333947862
Short name T665
Test name
Test status
Simulation time 88789589 ps
CPU time 3.28 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:15 PM PDT 24
Peak memory 198144 kb
Host smart-24f877b3-6129-4b26-aa6e-66b29f825eb7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333947862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3333947862
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1003074002
Short name T598
Test name
Test status
Simulation time 217838172 ps
CPU time 1.96 seconds
Started Jun 09 01:37:05 PM PDT 24
Finished Jun 09 01:37:07 PM PDT 24
Peak memory 197016 kb
Host smart-e0206c0c-e6e1-438f-aa62-37079857464a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003074002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1003074002
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1470025098
Short name T262
Test name
Test status
Simulation time 49764328 ps
CPU time 0.66 seconds
Started Jun 09 01:37:07 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 194404 kb
Host smart-c0b088e8-56f5-4c8a-a959-08b452b840e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470025098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1470025098
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2344164811
Short name T701
Test name
Test status
Simulation time 31888011 ps
CPU time 1.36 seconds
Started Jun 09 01:37:04 PM PDT 24
Finished Jun 09 01:37:06 PM PDT 24
Peak memory 198072 kb
Host smart-1c95597e-654a-4e87-b38c-27faec0c7a4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344164811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2344164811
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4041512407
Short name T645
Test name
Test status
Simulation time 68736403 ps
CPU time 3.43 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:15 PM PDT 24
Peak memory 197992 kb
Host smart-e704cf66-7957-4392-b2ec-894d14765ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041512407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4041512407
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.572419385
Short name T620
Test name
Test status
Simulation time 230035143 ps
CPU time 1.15 seconds
Started Jun 09 01:37:05 PM PDT 24
Finished Jun 09 01:37:06 PM PDT 24
Peak memory 195732 kb
Host smart-a98bafc8-7e40-4815-90c6-851fed5d84c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572419385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.572419385
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2920485975
Short name T554
Test name
Test status
Simulation time 73027703 ps
CPU time 1.05 seconds
Started Jun 09 01:37:06 PM PDT 24
Finished Jun 09 01:37:08 PM PDT 24
Peak memory 195572 kb
Host smart-bde7a680-f010-4943-bc16-c05e371e742a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920485975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2920485975
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2625614282
Short name T587
Test name
Test status
Simulation time 3676175103 ps
CPU time 39.09 seconds
Started Jun 09 01:37:12 PM PDT 24
Finished Jun 09 01:37:52 PM PDT 24
Peak memory 198220 kb
Host smart-d4151a3d-0d6c-47c1-b0b7-dd615f895334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625614282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2625614282
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.963149233
Short name T242
Test name
Test status
Simulation time 15533152 ps
CPU time 0.55 seconds
Started Jun 09 01:37:16 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 193956 kb
Host smart-4c65b06a-836c-4760-b6f5-4e6d9c764550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963149233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.963149233
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2922940116
Short name T311
Test name
Test status
Simulation time 91770137 ps
CPU time 0.93 seconds
Started Jun 09 01:37:12 PM PDT 24
Finished Jun 09 01:37:13 PM PDT 24
Peak memory 197424 kb
Host smart-f64eba8d-efac-4d7e-9211-9c12d17e4e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922940116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2922940116
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.4196936016
Short name T549
Test name
Test status
Simulation time 260242520 ps
CPU time 3.44 seconds
Started Jun 09 01:37:13 PM PDT 24
Finished Jun 09 01:37:16 PM PDT 24
Peak memory 195944 kb
Host smart-eed48379-2fb0-488b-8537-9cd882750df0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196936016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.4196936016
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.867278419
Short name T124
Test name
Test status
Simulation time 484602307 ps
CPU time 0.9 seconds
Started Jun 09 01:37:15 PM PDT 24
Finished Jun 09 01:37:16 PM PDT 24
Peak memory 197232 kb
Host smart-01455db4-6bca-4250-80f4-8b88fa64c73f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867278419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.867278419
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3183076274
Short name T649
Test name
Test status
Simulation time 18544724 ps
CPU time 0.68 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:12 PM PDT 24
Peak memory 194352 kb
Host smart-364d8e4b-b7e3-4070-9f0a-7c553f0074b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183076274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3183076274
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2080303768
Short name T608
Test name
Test status
Simulation time 75590647 ps
CPU time 2.86 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:14 PM PDT 24
Peak memory 198080 kb
Host smart-54f32d53-304c-47f9-8481-604a5128e8c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080303768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2080303768
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.4293124649
Short name T522
Test name
Test status
Simulation time 180328881 ps
CPU time 1.74 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:13 PM PDT 24
Peak memory 196516 kb
Host smart-b00afea9-9a7d-4e41-80d9-87cbfefb481f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293124649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.4293124649
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3835310109
Short name T670
Test name
Test status
Simulation time 68582051 ps
CPU time 0.88 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:13 PM PDT 24
Peak memory 196664 kb
Host smart-21ab3e25-df79-4d63-a905-d0c0bb4aad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835310109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3835310109
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3908413691
Short name T595
Test name
Test status
Simulation time 73288549 ps
CPU time 0.68 seconds
Started Jun 09 01:37:10 PM PDT 24
Finished Jun 09 01:37:11 PM PDT 24
Peak memory 194360 kb
Host smart-1bb399ef-8642-4311-96a5-01eb7002cf57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908413691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3908413691
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3959485243
Short name T601
Test name
Test status
Simulation time 1479963542 ps
CPU time 4.14 seconds
Started Jun 09 01:37:19 PM PDT 24
Finished Jun 09 01:37:23 PM PDT 24
Peak memory 197984 kb
Host smart-64d5b4ca-6a8c-4725-9d6f-851dd1c2a382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959485243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3959485243
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2844003251
Short name T126
Test name
Test status
Simulation time 29972930 ps
CPU time 0.95 seconds
Started Jun 09 01:37:11 PM PDT 24
Finished Jun 09 01:37:12 PM PDT 24
Peak memory 196620 kb
Host smart-0f8bab6f-a358-465d-80b7-ff114863d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844003251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2844003251
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4143597463
Short name T381
Test name
Test status
Simulation time 100165670 ps
CPU time 1.15 seconds
Started Jun 09 01:37:12 PM PDT 24
Finished Jun 09 01:37:13 PM PDT 24
Peak memory 195916 kb
Host smart-361590b9-26a5-4901-a167-13a81bb36e64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143597463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4143597463
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.901425462
Short name T273
Test name
Test status
Simulation time 5558934759 ps
CPU time 79 seconds
Started Jun 09 01:37:20 PM PDT 24
Finished Jun 09 01:38:39 PM PDT 24
Peak memory 198276 kb
Host smart-7357e8dc-479d-4f9e-970d-9d475bbcb71d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901425462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.901425462
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1680454331
Short name T384
Test name
Test status
Simulation time 39254134 ps
CPU time 0.56 seconds
Started Jun 09 01:37:20 PM PDT 24
Finished Jun 09 01:37:20 PM PDT 24
Peak memory 193972 kb
Host smart-ad9d2964-6073-49bc-a3ca-12b831001d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680454331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1680454331
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2522706394
Short name T325
Test name
Test status
Simulation time 29205906 ps
CPU time 0.86 seconds
Started Jun 09 01:37:19 PM PDT 24
Finished Jun 09 01:37:20 PM PDT 24
Peak memory 196604 kb
Host smart-7fe70e33-d9ba-4b13-983b-72aaf1cc36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522706394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2522706394
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2930053
Short name T110
Test name
Test status
Simulation time 370260627 ps
CPU time 6.42 seconds
Started Jun 09 01:37:14 PM PDT 24
Finished Jun 09 01:37:21 PM PDT 24
Peak memory 196280 kb
Host smart-b10d44c9-00f1-49a7-8235-71b03b02e913
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress.2930053
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3874368245
Short name T615
Test name
Test status
Simulation time 235771256 ps
CPU time 1.1 seconds
Started Jun 09 01:37:18 PM PDT 24
Finished Jun 09 01:37:19 PM PDT 24
Peak memory 197928 kb
Host smart-9ebf81b2-1203-4b56-aeac-70a0ac749f70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874368245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3874368245
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3931607116
Short name T507
Test name
Test status
Simulation time 107606575 ps
CPU time 0.9 seconds
Started Jun 09 01:37:16 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 196116 kb
Host smart-8e4821e0-ae3f-4196-b4f9-97c20fecb901
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931607116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3931607116
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.995901257
Short name T323
Test name
Test status
Simulation time 221105682 ps
CPU time 2.24 seconds
Started Jun 09 01:37:15 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 198244 kb
Host smart-e13777ea-929e-4698-be1c-186b49259af2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995901257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.995901257
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.575982755
Short name T252
Test name
Test status
Simulation time 685624477 ps
CPU time 3.19 seconds
Started Jun 09 01:37:18 PM PDT 24
Finished Jun 09 01:37:21 PM PDT 24
Peak memory 197180 kb
Host smart-c4a5dc4f-6790-4c82-b844-5004c71abb38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575982755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
575982755
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1802766039
Short name T54
Test name
Test status
Simulation time 874493968 ps
CPU time 1.1 seconds
Started Jun 09 01:37:28 PM PDT 24
Finished Jun 09 01:37:30 PM PDT 24
Peak memory 196668 kb
Host smart-259b28a2-538b-4ab7-a37f-e50123168820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802766039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1802766039
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1239759484
Short name T284
Test name
Test status
Simulation time 32035704 ps
CPU time 0.85 seconds
Started Jun 09 01:37:18 PM PDT 24
Finished Jun 09 01:37:19 PM PDT 24
Peak memory 196116 kb
Host smart-5d9a1146-2076-4822-9456-fc5cac948747
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239759484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1239759484
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4158352563
Short name T278
Test name
Test status
Simulation time 54463740 ps
CPU time 2.38 seconds
Started Jun 09 01:37:29 PM PDT 24
Finished Jun 09 01:37:32 PM PDT 24
Peak memory 198008 kb
Host smart-6b28a374-e37d-4c40-84f9-a82b1f234a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158352563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4158352563
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2520911992
Short name T271
Test name
Test status
Simulation time 49509765 ps
CPU time 1.32 seconds
Started Jun 09 01:37:30 PM PDT 24
Finished Jun 09 01:37:32 PM PDT 24
Peak memory 196728 kb
Host smart-7080599e-8738-4d97-b5f3-4d825898b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520911992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2520911992
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3578777097
Short name T607
Test name
Test status
Simulation time 136367050 ps
CPU time 1.21 seconds
Started Jun 09 01:37:19 PM PDT 24
Finished Jun 09 01:37:21 PM PDT 24
Peak memory 195592 kb
Host smart-70bb13b0-f50c-4523-93fc-321032339c03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578777097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3578777097
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2797015596
Short name T476
Test name
Test status
Simulation time 8674832079 ps
CPU time 94.3 seconds
Started Jun 09 01:37:17 PM PDT 24
Finished Jun 09 01:38:52 PM PDT 24
Peak memory 198200 kb
Host smart-383c8ed3-a897-4c31-8bbb-61c1ac327347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797015596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2797015596
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1443761102
Short name T390
Test name
Test status
Simulation time 43401352 ps
CPU time 0.57 seconds
Started Jun 09 01:37:26 PM PDT 24
Finished Jun 09 01:37:27 PM PDT 24
Peak memory 194136 kb
Host smart-d94b3d43-9a40-499a-82d4-034ba7a1e7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443761102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1443761102
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.624415978
Short name T186
Test name
Test status
Simulation time 17376441 ps
CPU time 0.67 seconds
Started Jun 09 01:37:14 PM PDT 24
Finished Jun 09 01:37:14 PM PDT 24
Peak memory 194152 kb
Host smart-33bfc080-05a0-4e88-b671-73daa6f71eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624415978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.624415978
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2441824150
Short name T671
Test name
Test status
Simulation time 1631453253 ps
CPU time 27.62 seconds
Started Jun 09 01:37:30 PM PDT 24
Finished Jun 09 01:37:58 PM PDT 24
Peak memory 196260 kb
Host smart-c27fd155-63db-4ee7-8a13-dc3ee1f69ab9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441824150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2441824150
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1045934926
Short name T475
Test name
Test status
Simulation time 78596143 ps
CPU time 0.91 seconds
Started Jun 09 01:37:30 PM PDT 24
Finished Jun 09 01:37:31 PM PDT 24
Peak memory 196568 kb
Host smart-08818bb7-8d15-44bb-84a8-2bfaf2765a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045934926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1045934926
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.185781423
Short name T469
Test name
Test status
Simulation time 70787727 ps
CPU time 2.69 seconds
Started Jun 09 01:37:20 PM PDT 24
Finished Jun 09 01:37:23 PM PDT 24
Peak memory 198084 kb
Host smart-519ae785-a0e9-49e7-8ff4-3bc1479ba4c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185781423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.185781423
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3624663816
Short name T663
Test name
Test status
Simulation time 242282825 ps
CPU time 3.68 seconds
Started Jun 09 01:37:15 PM PDT 24
Finished Jun 09 01:37:19 PM PDT 24
Peak memory 196688 kb
Host smart-37854b6c-d7c8-4f3b-840c-679b86143854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624663816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3624663816
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3696978857
Short name T364
Test name
Test status
Simulation time 126534896 ps
CPU time 0.79 seconds
Started Jun 09 01:37:16 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 195576 kb
Host smart-f24dbd40-41f4-48ae-9448-5bcbc46201f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696978857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3696978857
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2752138295
Short name T174
Test name
Test status
Simulation time 63794497 ps
CPU time 0.67 seconds
Started Jun 09 01:37:19 PM PDT 24
Finished Jun 09 01:37:20 PM PDT 24
Peak memory 194404 kb
Host smart-8d0f0f3d-b47d-4298-852f-5a3e1255ac2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752138295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2752138295
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2880185689
Short name T10
Test name
Test status
Simulation time 273358691 ps
CPU time 3.79 seconds
Started Jun 09 01:37:17 PM PDT 24
Finished Jun 09 01:37:21 PM PDT 24
Peak memory 197844 kb
Host smart-61eb4db6-0d0d-4835-83b3-84827fc05cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880185689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2880185689
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1207479528
Short name T184
Test name
Test status
Simulation time 343257872 ps
CPU time 1.35 seconds
Started Jun 09 01:37:16 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 196820 kb
Host smart-0053e05b-00d5-4145-9585-2062718e775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207479528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1207479528
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2124786048
Short name T402
Test name
Test status
Simulation time 145360944 ps
CPU time 1.12 seconds
Started Jun 09 01:37:30 PM PDT 24
Finished Jun 09 01:37:31 PM PDT 24
Peak memory 195536 kb
Host smart-7ef7c70b-39ca-4002-a608-b1af6d355d10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124786048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2124786048
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2731217936
Short name T172
Test name
Test status
Simulation time 2191356888 ps
CPU time 29.1 seconds
Started Jun 09 01:37:23 PM PDT 24
Finished Jun 09 01:37:52 PM PDT 24
Peak memory 198132 kb
Host smart-4e14884a-1d37-4402-823f-164b08543d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731217936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2731217936
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1233108968
Short name T403
Test name
Test status
Simulation time 81889374040 ps
CPU time 394.76 seconds
Started Jun 09 01:37:23 PM PDT 24
Finished Jun 09 01:43:58 PM PDT 24
Peak memory 198272 kb
Host smart-59f25085-cbb0-4e6e-8847-94eecb47ca34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1233108968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1233108968
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3078801528
Short name T348
Test name
Test status
Simulation time 55402486 ps
CPU time 0.58 seconds
Started Jun 09 01:34:34 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 194128 kb
Host smart-2fe1cc3e-236a-4f39-80b4-8bd2615c4a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078801528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3078801528
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.447439802
Short name T531
Test name
Test status
Simulation time 186326481 ps
CPU time 0.9 seconds
Started Jun 09 01:34:34 PM PDT 24
Finished Jun 09 01:34:36 PM PDT 24
Peak memory 196544 kb
Host smart-34e29699-d083-4e7e-bbe7-feb95e8966ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447439802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.447439802
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2966009791
Short name T618
Test name
Test status
Simulation time 1465885998 ps
CPU time 13.4 seconds
Started Jun 09 01:34:33 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 197140 kb
Host smart-99e8acdc-03ee-4080-ba3f-d7e2641e9159
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966009791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2966009791
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2455215453
Short name T577
Test name
Test status
Simulation time 88293086 ps
CPU time 0.63 seconds
Started Jun 09 01:34:31 PM PDT 24
Finished Jun 09 01:34:32 PM PDT 24
Peak memory 194616 kb
Host smart-754eadd1-2e15-4669-ae56-4e212db86ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455215453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2455215453
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.979020638
Short name T120
Test name
Test status
Simulation time 297674065 ps
CPU time 1.28 seconds
Started Jun 09 01:34:32 PM PDT 24
Finished Jun 09 01:34:33 PM PDT 24
Peak memory 197048 kb
Host smart-d80f1712-02ec-4249-8714-a409dbe68a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979020638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.979020638
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2387442605
Short name T561
Test name
Test status
Simulation time 349062675 ps
CPU time 2.53 seconds
Started Jun 09 01:34:35 PM PDT 24
Finished Jun 09 01:34:38 PM PDT 24
Peak memory 196376 kb
Host smart-96ff7ff2-3836-4e99-8b56-3f5c10a9b074
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387442605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2387442605
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3717458295
Short name T451
Test name
Test status
Simulation time 450964847 ps
CPU time 2.54 seconds
Started Jun 09 01:34:35 PM PDT 24
Finished Jun 09 01:34:38 PM PDT 24
Peak memory 197132 kb
Host smart-e1bb6b2f-d126-4d79-bc7a-75ce97c9c81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717458295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3717458295
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3284463712
Short name T147
Test name
Test status
Simulation time 103976474 ps
CPU time 1.02 seconds
Started Jun 09 01:34:32 PM PDT 24
Finished Jun 09 01:34:34 PM PDT 24
Peak memory 196796 kb
Host smart-171d6f29-26a7-4c98-be10-b52a794f865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284463712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3284463712
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1211404284
Short name T280
Test name
Test status
Simulation time 31535072 ps
CPU time 1.18 seconds
Started Jun 09 01:34:31 PM PDT 24
Finished Jun 09 01:34:32 PM PDT 24
Peak memory 195840 kb
Host smart-c1c04a33-e51e-49ff-a879-7611a6a7a44b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211404284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1211404284
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3083657813
Short name T156
Test name
Test status
Simulation time 72915922 ps
CPU time 1.31 seconds
Started Jun 09 01:34:31 PM PDT 24
Finished Jun 09 01:34:33 PM PDT 24
Peak memory 197972 kb
Host smart-a75778ff-522d-4a73-ba31-6642f3b7c64f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083657813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3083657813
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.974647267
Short name T638
Test name
Test status
Simulation time 209559298 ps
CPU time 1.13 seconds
Started Jun 09 01:34:28 PM PDT 24
Finished Jun 09 01:34:29 PM PDT 24
Peak memory 195804 kb
Host smart-75447c60-213a-4956-b33e-dfa11dea0ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974647267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.974647267
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1661385299
Short name T391
Test name
Test status
Simulation time 106136451 ps
CPU time 0.89 seconds
Started Jun 09 01:34:31 PM PDT 24
Finished Jun 09 01:34:32 PM PDT 24
Peak memory 196580 kb
Host smart-0170c8c4-a346-469c-89a8-bd95d193fc27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661385299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1661385299
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3313832929
Short name T18
Test name
Test status
Simulation time 27124270498 ps
CPU time 272.61 seconds
Started Jun 09 01:34:32 PM PDT 24
Finished Jun 09 01:39:05 PM PDT 24
Peak memory 198180 kb
Host smart-4b19df3f-c84a-4a06-a665-efbb851a4a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313832929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3313832929
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1351823743
Short name T655
Test name
Test status
Simulation time 19553092 ps
CPU time 0.56 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:45 PM PDT 24
Peak memory 193908 kb
Host smart-d3549ba6-4b3d-4dc4-8517-32029a5c0d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351823743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1351823743
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3005941690
Short name T260
Test name
Test status
Simulation time 34568269 ps
CPU time 0.85 seconds
Started Jun 09 01:34:32 PM PDT 24
Finished Jun 09 01:34:33 PM PDT 24
Peak memory 195364 kb
Host smart-1eddd9d6-4d62-4586-a7ae-bef975a799c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005941690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3005941690
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3239156294
Short name T698
Test name
Test status
Simulation time 280461309 ps
CPU time 15.05 seconds
Started Jun 09 01:34:38 PM PDT 24
Finished Jun 09 01:34:53 PM PDT 24
Peak memory 196464 kb
Host smart-d2425f58-73fe-4ee4-ad25-7af86ae2e05e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239156294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3239156294
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4212201473
Short name T367
Test name
Test status
Simulation time 66981302 ps
CPU time 0.91 seconds
Started Jun 09 01:34:43 PM PDT 24
Finished Jun 09 01:34:44 PM PDT 24
Peak memory 197056 kb
Host smart-6427bf2a-aa81-4fb2-a02b-b16f384d6982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212201473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4212201473
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.618110464
Short name T143
Test name
Test status
Simulation time 17109523 ps
CPU time 0.69 seconds
Started Jun 09 01:34:34 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 194328 kb
Host smart-f1e7a9c8-1920-4bc9-8eba-3441b9fc1779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618110464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.618110464
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2999821254
Short name T359
Test name
Test status
Simulation time 357595409 ps
CPU time 3.41 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:34:51 PM PDT 24
Peak memory 198040 kb
Host smart-aedb02bc-28bd-4f5b-98a6-cbffe269254f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999821254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2999821254
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2952832681
Short name T538
Test name
Test status
Simulation time 603456633 ps
CPU time 3.38 seconds
Started Jun 09 01:34:35 PM PDT 24
Finished Jun 09 01:34:39 PM PDT 24
Peak memory 195912 kb
Host smart-6140be91-395c-4ce1-bb8c-a6137d000509
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952832681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2952832681
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.611422527
Short name T516
Test name
Test status
Simulation time 33768441 ps
CPU time 0.9 seconds
Started Jun 09 01:34:35 PM PDT 24
Finished Jun 09 01:34:36 PM PDT 24
Peak memory 195840 kb
Host smart-8595e4e0-f7d3-4503-a193-53ee01edc00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611422527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.611422527
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3468942550
Short name T291
Test name
Test status
Simulation time 102772736 ps
CPU time 1.03 seconds
Started Jun 09 01:34:33 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 195928 kb
Host smart-292151e9-7435-40ca-a834-41a3a2595b4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468942550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3468942550
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3013803399
Short name T312
Test name
Test status
Simulation time 79200208 ps
CPU time 1.34 seconds
Started Jun 09 01:34:43 PM PDT 24
Finished Jun 09 01:34:45 PM PDT 24
Peak memory 197936 kb
Host smart-43b1fc6c-773f-41f7-a7c0-bb68cb959b91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013803399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3013803399
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2952042640
Short name T636
Test name
Test status
Simulation time 141037412 ps
CPU time 1.01 seconds
Started Jun 09 01:34:32 PM PDT 24
Finished Jun 09 01:34:33 PM PDT 24
Peak memory 195648 kb
Host smart-991fd5eb-99f5-40c4-bb14-d738a3c0c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952042640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2952042640
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4120180452
Short name T355
Test name
Test status
Simulation time 231568510 ps
CPU time 1.29 seconds
Started Jun 09 01:34:34 PM PDT 24
Finished Jun 09 01:34:35 PM PDT 24
Peak memory 195924 kb
Host smart-7c1d006a-af9c-4fdd-8c9e-d3642c45bd25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120180452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4120180452
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3258437874
Short name T26
Test name
Test status
Simulation time 12095606651 ps
CPU time 172.16 seconds
Started Jun 09 01:34:38 PM PDT 24
Finished Jun 09 01:37:30 PM PDT 24
Peak memory 198452 kb
Host smart-a1ebfe1e-5e36-4957-a12b-5569a98e74b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258437874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3258437874
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.407781108
Short name T92
Test name
Test status
Simulation time 379909010789 ps
CPU time 3066.22 seconds
Started Jun 09 01:34:45 PM PDT 24
Finished Jun 09 02:25:52 PM PDT 24
Peak memory 198216 kb
Host smart-cc983488-5863-4476-a575-23eca3373e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=407781108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.407781108
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3070867656
Short name T664
Test name
Test status
Simulation time 14859455 ps
CPU time 0.6 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:34:47 PM PDT 24
Peak memory 194132 kb
Host smart-ddc9f357-2f10-4ea4-96d7-6f0c5b93086c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070867656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3070867656
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4069152861
Short name T461
Test name
Test status
Simulation time 25081955 ps
CPU time 0.69 seconds
Started Jun 09 01:34:43 PM PDT 24
Finished Jun 09 01:34:44 PM PDT 24
Peak memory 194956 kb
Host smart-8e47b35f-e6a8-4fa3-90dd-581bf22c8cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069152861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4069152861
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.942162852
Short name T340
Test name
Test status
Simulation time 859729350 ps
CPU time 22.7 seconds
Started Jun 09 01:34:39 PM PDT 24
Finished Jun 09 01:35:02 PM PDT 24
Peak memory 196316 kb
Host smart-e84e4f68-59ec-4036-987f-c64a1735f4a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942162852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.942162852
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3470739423
Short name T478
Test name
Test status
Simulation time 143047913 ps
CPU time 0.94 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 197388 kb
Host smart-6849a51b-6380-486f-b478-2c0fc4a6e796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470739423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3470739423
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.64803695
Short name T548
Test name
Test status
Simulation time 33789172 ps
CPU time 0.91 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:34:48 PM PDT 24
Peak memory 195828 kb
Host smart-b7f52dde-fdbb-4b1d-85f5-d8fc852af699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64803695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.64803695
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.470941114
Short name T362
Test name
Test status
Simulation time 129050873 ps
CPU time 1.46 seconds
Started Jun 09 01:34:43 PM PDT 24
Finished Jun 09 01:34:45 PM PDT 24
Peak memory 196572 kb
Host smart-4389982c-d55e-4eee-9a0f-2a7f25d0e3af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470941114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.470941114
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1890354317
Short name T493
Test name
Test status
Simulation time 84278891 ps
CPU time 2.28 seconds
Started Jun 09 01:34:46 PM PDT 24
Finished Jun 09 01:34:49 PM PDT 24
Peak memory 195832 kb
Host smart-02a97f9a-4ec5-4d45-919e-677eede7f1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890354317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1890354317
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.344237524
Short name T667
Test name
Test status
Simulation time 33068901 ps
CPU time 1.18 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 198132 kb
Host smart-238a3911-9eaf-4a0f-8d5a-84d1dee60490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344237524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.344237524
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2626026489
Short name T98
Test name
Test status
Simulation time 46917329 ps
CPU time 0.66 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:45 PM PDT 24
Peak memory 194592 kb
Host smart-21b72a35-deb6-426a-9a6e-87292b8f6a0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626026489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2626026489
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3466524316
Short name T564
Test name
Test status
Simulation time 365294010 ps
CPU time 3.97 seconds
Started Jun 09 01:34:46 PM PDT 24
Finished Jun 09 01:34:50 PM PDT 24
Peak memory 197992 kb
Host smart-328db62b-33c3-481a-a601-6b42b36c6502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466524316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3466524316
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3046935757
Short name T144
Test name
Test status
Simulation time 337849856 ps
CPU time 1.13 seconds
Started Jun 09 01:34:43 PM PDT 24
Finished Jun 09 01:34:44 PM PDT 24
Peak memory 196528 kb
Host smart-2a2d1bef-b8ea-4f9f-8b2b-44e2547ac197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046935757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3046935757
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2294667829
Short name T400
Test name
Test status
Simulation time 117607142 ps
CPU time 1.47 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 196760 kb
Host smart-552d0582-b0f1-4fa9-9e8b-3bfe5603b07a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294667829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2294667829
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1160294587
Short name T4
Test name
Test status
Simulation time 14504394991 ps
CPU time 193.66 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:38:01 PM PDT 24
Peak memory 198168 kb
Host smart-975bd77a-98a1-4e4a-b314-405cabee0661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160294587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1160294587
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.217786132
Short name T296
Test name
Test status
Simulation time 26786378 ps
CPU time 0.55 seconds
Started Jun 09 01:34:48 PM PDT 24
Finished Jun 09 01:34:49 PM PDT 24
Peak memory 194628 kb
Host smart-0cb80f06-0472-4331-8215-f31dcb7b0026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217786132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.217786132
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.571732318
Short name T25
Test name
Test status
Simulation time 66625414 ps
CPU time 0.9 seconds
Started Jun 09 01:34:46 PM PDT 24
Finished Jun 09 01:34:48 PM PDT 24
Peak memory 196208 kb
Host smart-8226a326-cc7e-421e-88a6-905d681736a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571732318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.571732318
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1402918362
Short name T115
Test name
Test status
Simulation time 2358658607 ps
CPU time 19.45 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:35:04 PM PDT 24
Peak memory 198164 kb
Host smart-19ad3480-5ebc-4246-9e7f-442af5256335
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402918362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1402918362
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3732365286
Short name T687
Test name
Test status
Simulation time 290200496 ps
CPU time 0.92 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 197308 kb
Host smart-f2ed232e-4888-424b-a7c9-4742494a67e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732365286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3732365286
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1184682254
Short name T203
Test name
Test status
Simulation time 99629726 ps
CPU time 1.38 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 198076 kb
Host smart-ed62027c-765f-4f68-9aea-4f63540e2d06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184682254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1184682254
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1235886296
Short name T269
Test name
Test status
Simulation time 106805245 ps
CPU time 2.14 seconds
Started Jun 09 01:34:46 PM PDT 24
Finished Jun 09 01:34:49 PM PDT 24
Peak memory 198008 kb
Host smart-0f14c902-7cd7-4926-afba-d60b6e264cf7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235886296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1235886296
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3712576799
Short name T704
Test name
Test status
Simulation time 170341939 ps
CPU time 3.2 seconds
Started Jun 09 01:34:46 PM PDT 24
Finished Jun 09 01:34:50 PM PDT 24
Peak memory 196752 kb
Host smart-edc387d0-6927-4d5e-93e4-161124f8d948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712576799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3712576799
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2482281168
Short name T496
Test name
Test status
Simulation time 52260275 ps
CPU time 1.21 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 195804 kb
Host smart-c1365b3a-204c-448f-bc18-e0027f32e9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482281168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2482281168
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.722068780
Short name T393
Test name
Test status
Simulation time 250514937 ps
CPU time 1.3 seconds
Started Jun 09 01:34:46 PM PDT 24
Finished Jun 09 01:34:48 PM PDT 24
Peak memory 195852 kb
Host smart-a57f839e-2f6f-4837-b088-426201c63a11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722068780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.722068780
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.351591486
Short name T62
Test name
Test status
Simulation time 73463602 ps
CPU time 1.54 seconds
Started Jun 09 01:34:45 PM PDT 24
Finished Jun 09 01:34:47 PM PDT 24
Peak memory 198076 kb
Host smart-92ef0832-044f-43c8-8f5a-108a57eceb40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351591486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.351591486
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1083248134
Short name T282
Test name
Test status
Simulation time 67965066 ps
CPU time 1.08 seconds
Started Jun 09 01:34:44 PM PDT 24
Finished Jun 09 01:34:45 PM PDT 24
Peak memory 195804 kb
Host smart-8bcd9fad-e04f-4598-b7c9-7fd68cf464c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083248134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1083248134
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3041412162
Short name T503
Test name
Test status
Simulation time 133015210 ps
CPU time 0.95 seconds
Started Jun 09 01:34:45 PM PDT 24
Finished Jun 09 01:34:47 PM PDT 24
Peak memory 196484 kb
Host smart-4043f881-caf9-45a3-a337-41fcc2cffce0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041412162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3041412162
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1609299151
Short name T344
Test name
Test status
Simulation time 7593778617 ps
CPU time 111.49 seconds
Started Jun 09 01:34:45 PM PDT 24
Finished Jun 09 01:36:37 PM PDT 24
Peak memory 198212 kb
Host smart-0ade0374-d070-404e-b8ec-f9ebddb77ba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609299151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1609299151
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3420099811
Short name T388
Test name
Test status
Simulation time 387915729186 ps
CPU time 684.07 seconds
Started Jun 09 01:34:45 PM PDT 24
Finished Jun 09 01:46:10 PM PDT 24
Peak memory 198276 kb
Host smart-fe6dc3e6-3071-4062-8d45-d9426c4ead1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3420099811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3420099811
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.882875668
Short name T624
Test name
Test status
Simulation time 14572152 ps
CPU time 0.55 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:54 PM PDT 24
Peak memory 192788 kb
Host smart-aa2cbf5c-d8ec-4f5c-a523-0ef2d4801161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882875668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.882875668
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2730465821
Short name T13
Test name
Test status
Simulation time 106194220 ps
CPU time 0.56 seconds
Started Jun 09 01:34:49 PM PDT 24
Finished Jun 09 01:34:50 PM PDT 24
Peak memory 194000 kb
Host smart-20e194ba-49b2-4c40-935b-8c529c4fdb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730465821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2730465821
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2843770847
Short name T657
Test name
Test status
Simulation time 176821121 ps
CPU time 9.58 seconds
Started Jun 09 01:34:49 PM PDT 24
Finished Jun 09 01:34:59 PM PDT 24
Peak memory 196716 kb
Host smart-4668f01f-6dd1-4861-bb96-13733e065232
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843770847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2843770847
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3227735042
Short name T22
Test name
Test status
Simulation time 175924339 ps
CPU time 0.84 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:34:48 PM PDT 24
Peak memory 196040 kb
Host smart-dfcc4f8d-f0c9-4d82-bad0-925c4a1c0d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227735042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3227735042
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3714293869
Short name T428
Test name
Test status
Simulation time 396425160 ps
CPU time 1.21 seconds
Started Jun 09 01:34:49 PM PDT 24
Finished Jun 09 01:34:50 PM PDT 24
Peak memory 196000 kb
Host smart-f976de9e-da70-47d5-b928-a4dea65a773c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714293869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3714293869
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3095233953
Short name T382
Test name
Test status
Simulation time 48424644 ps
CPU time 2.11 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:34:50 PM PDT 24
Peak memory 198080 kb
Host smart-585446cf-9873-4772-bdce-48e729fa6d96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095233953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3095233953
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1179787966
Short name T501
Test name
Test status
Simulation time 827703649 ps
CPU time 1.72 seconds
Started Jun 09 01:34:50 PM PDT 24
Finished Jun 09 01:34:52 PM PDT 24
Peak memory 196160 kb
Host smart-a8570fea-5622-4148-8ddd-6ef9125980b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179787966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1179787966
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3110143065
Short name T472
Test name
Test status
Simulation time 160937321 ps
CPU time 1.04 seconds
Started Jun 09 01:34:52 PM PDT 24
Finished Jun 09 01:34:53 PM PDT 24
Peak memory 196064 kb
Host smart-3a331e58-6dc8-4484-8aaf-535c67b38644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110143065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3110143065
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3426256625
Short name T211
Test name
Test status
Simulation time 200285673 ps
CPU time 1.07 seconds
Started Jun 09 01:34:50 PM PDT 24
Finished Jun 09 01:34:51 PM PDT 24
Peak memory 195996 kb
Host smart-cf84915a-cf2c-4dbc-a381-2201dc012502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426256625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3426256625
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.810339438
Short name T187
Test name
Test status
Simulation time 79160150 ps
CPU time 3.64 seconds
Started Jun 09 01:34:54 PM PDT 24
Finished Jun 09 01:34:58 PM PDT 24
Peak memory 197984 kb
Host smart-25921ac7-ed43-4db7-8f83-eaf7334d1c8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810339438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.810339438
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2204912107
Short name T234
Test name
Test status
Simulation time 118453706 ps
CPU time 0.81 seconds
Started Jun 09 01:34:49 PM PDT 24
Finished Jun 09 01:34:50 PM PDT 24
Peak memory 195280 kb
Host smart-9dbbbe10-41c2-43b5-b12e-4458f3fcc47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204912107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2204912107
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3406584476
Short name T673
Test name
Test status
Simulation time 47722073 ps
CPU time 1.38 seconds
Started Jun 09 01:34:47 PM PDT 24
Finished Jun 09 01:34:49 PM PDT 24
Peak memory 196840 kb
Host smart-660f5dc0-7803-449e-a20f-d198d6485533
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406584476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3406584476
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.4012350090
Short name T122
Test name
Test status
Simulation time 6864860037 ps
CPU time 150.23 seconds
Started Jun 09 01:34:52 PM PDT 24
Finished Jun 09 01:37:22 PM PDT 24
Peak memory 198192 kb
Host smart-1f78984c-73fd-4cfb-b2c8-2e3723c7f76d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012350090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.4012350090
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3048344161
Short name T861
Test name
Test status
Simulation time 131700892 ps
CPU time 1.06 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 196076 kb
Host smart-0c502f72-c4ee-46b5-a7d9-b878cb6281fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3048344161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3048344161
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2598763521
Short name T877
Test name
Test status
Simulation time 298203436 ps
CPU time 0.82 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 195732 kb
Host smart-bf6626e9-9423-4a6a-a87d-cb0285e3b34b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598763521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2598763521
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1428504628
Short name T908
Test name
Test status
Simulation time 96670495 ps
CPU time 0.9 seconds
Started Jun 09 12:33:15 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 196676 kb
Host smart-a4ec2aeb-5ecb-41fc-b32a-990e29b0b673
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1428504628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1428504628
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.530856474
Short name T938
Test name
Test status
Simulation time 47828136 ps
CPU time 0.94 seconds
Started Jun 09 12:33:10 PM PDT 24
Finished Jun 09 12:33:12 PM PDT 24
Peak memory 197184 kb
Host smart-b4a0cc60-aa9d-4371-8d4f-9f216ba2d302
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530856474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.530856474
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3853841724
Short name T865
Test name
Test status
Simulation time 71314885 ps
CPU time 1.12 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196720 kb
Host smart-67ed10f6-e683-4958-a62f-4d6b2c1c210f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3853841724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3853841724
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1947863161
Short name T855
Test name
Test status
Simulation time 325270972 ps
CPU time 1.34 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 198080 kb
Host smart-b5266757-36a9-4201-ac3b-fad1e9aeeae9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947863161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1947863161
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.105505841
Short name T867
Test name
Test status
Simulation time 179830772 ps
CPU time 0.98 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 196444 kb
Host smart-daf18c60-7f85-4daa-b8e4-d9f0f069a778
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=105505841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.105505841
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1781035127
Short name T882
Test name
Test status
Simulation time 81001126 ps
CPU time 0.96 seconds
Started Jun 09 12:33:11 PM PDT 24
Finished Jun 09 12:33:12 PM PDT 24
Peak memory 198004 kb
Host smart-bee79c55-4bf5-4281-bf16-f0cf00fecc88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781035127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1781035127
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3692289782
Short name T891
Test name
Test status
Simulation time 304127343 ps
CPU time 1.28 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 196696 kb
Host smart-0cd65412-6242-4d40-860c-d6842e054f5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3692289782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3692289782
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1289000658
Short name T849
Test name
Test status
Simulation time 43852827 ps
CPU time 1.24 seconds
Started Jun 09 12:33:09 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 198188 kb
Host smart-0fd2b816-a55f-4f69-a002-70e66061f155
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289000658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1289000658
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1405753404
Short name T876
Test name
Test status
Simulation time 145143374 ps
CPU time 1.04 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 196804 kb
Host smart-b343398d-9c1a-4aac-9b83-5b19d8b1caf3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1405753404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1405753404
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1884339031
Short name T922
Test name
Test status
Simulation time 200357231 ps
CPU time 0.82 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 195644 kb
Host smart-d7e9c6d9-a212-4fa0-b6a1-9d023c3d0a14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884339031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1884339031
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.828739017
Short name T942
Test name
Test status
Simulation time 54185605 ps
CPU time 1.14 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 198172 kb
Host smart-0f324ffb-5720-491f-9d25-f61b0c68a3f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=828739017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.828739017
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3868502871
Short name T941
Test name
Test status
Simulation time 58083314 ps
CPU time 1.22 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 198124 kb
Host smart-934262e4-8c6c-4b2c-821e-f1469b50a469
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868502871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3868502871
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4210100402
Short name T862
Test name
Test status
Simulation time 86688928 ps
CPU time 1.31 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 196808 kb
Host smart-0b02447a-839d-4ee9-a4ee-81854a349b93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4210100402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.4210100402
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3507392388
Short name T864
Test name
Test status
Simulation time 129233260 ps
CPU time 0.89 seconds
Started Jun 09 12:33:08 PM PDT 24
Finished Jun 09 12:33:10 PM PDT 24
Peak memory 196348 kb
Host smart-2ca9cb39-9b2c-41d6-9bfb-9320fc6f33fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507392388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3507392388
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3413787958
Short name T893
Test name
Test status
Simulation time 594000996 ps
CPU time 1.26 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196076 kb
Host smart-f9608fae-b7bd-44bb-b2af-b6ac3fe4fdf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3413787958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3413787958
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2908816152
Short name T926
Test name
Test status
Simulation time 137744377 ps
CPU time 1.21 seconds
Started Jun 09 12:33:11 PM PDT 24
Finished Jun 09 12:33:12 PM PDT 24
Peak memory 198072 kb
Host smart-3bc2a2e9-d2df-402c-a9f2-85ce84155612
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908816152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2908816152
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3586117502
Short name T845
Test name
Test status
Simulation time 47765332 ps
CPU time 1.31 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 197004 kb
Host smart-0534deb3-1b87-4163-8d6c-279332189b77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3586117502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3586117502
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.745696396
Short name T896
Test name
Test status
Simulation time 63830411 ps
CPU time 0.99 seconds
Started Jun 09 12:33:10 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 195832 kb
Host smart-0b7e910e-6864-4563-98f1-2f8370eda0d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745696396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.745696396
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1444252285
Short name T923
Test name
Test status
Simulation time 190894888 ps
CPU time 1.35 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 197076 kb
Host smart-9058c38e-dc9c-47e1-893e-97dff68d2e82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1444252285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1444252285
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2915566707
Short name T886
Test name
Test status
Simulation time 69449807 ps
CPU time 1.4 seconds
Started Jun 09 12:33:08 PM PDT 24
Finished Jun 09 12:33:10 PM PDT 24
Peak memory 196764 kb
Host smart-721b2ba7-71d6-494b-874a-6c03801dfc72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915566707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2915566707
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.975263313
Short name T843
Test name
Test status
Simulation time 295663289 ps
CPU time 1.36 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:22 PM PDT 24
Peak memory 196716 kb
Host smart-70df5515-26fd-4af8-8ab8-8cb3fbaed3c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=975263313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.975263313
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.437081789
Short name T885
Test name
Test status
Simulation time 147526807 ps
CPU time 1.1 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 196080 kb
Host smart-6a08e4bd-78bb-43d9-b12c-2f71f68a76c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437081789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.437081789
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2449558067
Short name T875
Test name
Test status
Simulation time 102147368 ps
CPU time 1.44 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 198156 kb
Host smart-2ff44b25-488d-4ccb-9ef7-3c222bd55362
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2449558067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2449558067
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.265529800
Short name T902
Test name
Test status
Simulation time 206054148 ps
CPU time 1.07 seconds
Started Jun 09 12:33:15 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 195900 kb
Host smart-5a5f0349-d266-4c36-a0dc-017fc08cc887
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265529800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.265529800
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3643313185
Short name T851
Test name
Test status
Simulation time 105282839 ps
CPU time 1.38 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 196832 kb
Host smart-076ee189-362e-4cee-a20a-7d4118eab9fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3643313185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3643313185
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3083995131
Short name T910
Test name
Test status
Simulation time 240462373 ps
CPU time 1.06 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196096 kb
Host smart-a9615dea-9962-4af5-a891-a322a7640d66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083995131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3083995131
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.709889592
Short name T924
Test name
Test status
Simulation time 48041553 ps
CPU time 1.17 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 196932 kb
Host smart-5e60df43-b424-4a6f-ad66-b9e4ff4bfcfd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=709889592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.709889592
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1847742034
Short name T870
Test name
Test status
Simulation time 180925037 ps
CPU time 1.02 seconds
Started Jun 09 12:33:12 PM PDT 24
Finished Jun 09 12:33:13 PM PDT 24
Peak memory 196772 kb
Host smart-bd651ecc-0436-4552-a0ba-83c877278d72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847742034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1847742034
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2790502005
Short name T911
Test name
Test status
Simulation time 59645970 ps
CPU time 1.17 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 196652 kb
Host smart-cdb69b08-fbc2-494f-8374-040e9681d90c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2790502005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2790502005
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3407401440
Short name T930
Test name
Test status
Simulation time 184323274 ps
CPU time 0.8 seconds
Started Jun 09 12:33:04 PM PDT 24
Finished Jun 09 12:33:05 PM PDT 24
Peak memory 195624 kb
Host smart-c73766cc-cd8c-4214-8434-87c1d77c1011
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407401440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3407401440
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.232216200
Short name T917
Test name
Test status
Simulation time 149423218 ps
CPU time 0.94 seconds
Started Jun 09 12:33:25 PM PDT 24
Finished Jun 09 12:33:27 PM PDT 24
Peak memory 198172 kb
Host smart-5004863c-5bc7-4d63-bca3-bdc7a6783225
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=232216200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.232216200
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1851008729
Short name T887
Test name
Test status
Simulation time 344719267 ps
CPU time 1.43 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 195836 kb
Host smart-480d02eb-971f-4ef4-b65b-605b242a4bd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851008729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1851008729
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.138537811
Short name T903
Test name
Test status
Simulation time 60517534 ps
CPU time 0.75 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 195132 kb
Host smart-bff8f177-a2e3-4af0-80a2-d789379bf93a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=138537811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.138537811
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1818187507
Short name T920
Test name
Test status
Simulation time 94251867 ps
CPU time 1.2 seconds
Started Jun 09 12:33:10 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 196964 kb
Host smart-e55f51e0-25a8-438b-b8cd-78f2e2be9664
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818187507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1818187507
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2403839743
Short name T866
Test name
Test status
Simulation time 78548717 ps
CPU time 1.08 seconds
Started Jun 09 12:33:10 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 195976 kb
Host smart-392b9f3c-c6aa-47cc-bfcd-fcc6860f875c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2403839743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2403839743
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2960278296
Short name T883
Test name
Test status
Simulation time 50083524 ps
CPU time 0.96 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 197476 kb
Host smart-d56c6d94-82b2-4ce8-b8b6-63ecaee7ac94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960278296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2960278296
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4107692025
Short name T874
Test name
Test status
Simulation time 102474401 ps
CPU time 1.02 seconds
Started Jun 09 12:33:15 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 196824 kb
Host smart-63c976d8-873a-4762-be3d-c2239ee14ab0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4107692025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4107692025
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3419643042
Short name T935
Test name
Test status
Simulation time 161173907 ps
CPU time 0.88 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:22 PM PDT 24
Peak memory 196392 kb
Host smart-998d593a-fdbc-4c72-bfac-046ab73db870
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419643042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3419643042
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1065346340
Short name T900
Test name
Test status
Simulation time 99475746 ps
CPU time 0.97 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 197980 kb
Host smart-658f5ad1-e725-48b7-b505-06f0a50423d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1065346340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1065346340
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3355043563
Short name T888
Test name
Test status
Simulation time 117336387 ps
CPU time 0.93 seconds
Started Jun 09 12:33:09 PM PDT 24
Finished Jun 09 12:33:10 PM PDT 24
Peak memory 195504 kb
Host smart-af5a10f1-b41d-4fd4-ab7c-13f65fcab3e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355043563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3355043563
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3036100668
Short name T925
Test name
Test status
Simulation time 258841700 ps
CPU time 1.15 seconds
Started Jun 09 12:33:12 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 196080 kb
Host smart-490daa8d-905b-4449-9ff7-753246f72346
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3036100668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3036100668
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3262331143
Short name T904
Test name
Test status
Simulation time 45626127 ps
CPU time 0.93 seconds
Started Jun 09 12:33:15 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 196608 kb
Host smart-900e9e47-eb0a-4fba-bfa0-5ca36d780d29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262331143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3262331143
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.395971463
Short name T853
Test name
Test status
Simulation time 50460009 ps
CPU time 1.15 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 196576 kb
Host smart-7e19a360-eb4b-47f5-a5df-34e904875ae1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=395971463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.395971463
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470554191
Short name T906
Test name
Test status
Simulation time 59132261 ps
CPU time 1.14 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 196040 kb
Host smart-6a402c94-1108-4c02-b8f0-32967d4a251b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470554191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2470554191
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.942626561
Short name T931
Test name
Test status
Simulation time 150053582 ps
CPU time 1.15 seconds
Started Jun 09 12:33:11 PM PDT 24
Finished Jun 09 12:33:13 PM PDT 24
Peak memory 196788 kb
Host smart-10e13e15-2dbf-47a7-b1f0-a7a015a6a28a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=942626561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.942626561
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2282428730
Short name T871
Test name
Test status
Simulation time 243839364 ps
CPU time 1.06 seconds
Started Jun 09 12:33:10 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 196624 kb
Host smart-1d39ded9-d392-4c38-90ae-d4e6f9da8f4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282428730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2282428730
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3213611991
Short name T899
Test name
Test status
Simulation time 240419699 ps
CPU time 1.21 seconds
Started Jun 09 12:33:10 PM PDT 24
Finished Jun 09 12:33:12 PM PDT 24
Peak memory 198136 kb
Host smart-eb3bac44-c6f7-4c79-a451-de24f8b29f4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3213611991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3213611991
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1742362965
Short name T873
Test name
Test status
Simulation time 533974543 ps
CPU time 1 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196060 kb
Host smart-3e12af1a-54dd-41d5-a382-c93e6bdffb05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742362965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1742362965
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.481334724
Short name T916
Test name
Test status
Simulation time 47622547 ps
CPU time 0.99 seconds
Started Jun 09 12:33:15 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 196716 kb
Host smart-ea76a7a2-5851-472d-b286-bf01b63e4bfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=481334724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.481334724
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1000433456
Short name T848
Test name
Test status
Simulation time 280917964 ps
CPU time 1.25 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196616 kb
Host smart-b5fc1ae9-2dbb-45eb-97af-4ca5fd86dd4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000433456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1000433456
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3259926248
Short name T918
Test name
Test status
Simulation time 148160627 ps
CPU time 0.85 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:23 PM PDT 24
Peak memory 198076 kb
Host smart-9f1ad498-a190-492d-80fb-09eba9f6aa45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3259926248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3259926248
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3234883167
Short name T859
Test name
Test status
Simulation time 56685810 ps
CPU time 1.13 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 195844 kb
Host smart-4c79720e-bdf7-4126-b862-760d9cdd1528
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234883167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3234883167
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.551433699
Short name T932
Test name
Test status
Simulation time 43940044 ps
CPU time 1.26 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 198092 kb
Host smart-217f7ba5-f861-4205-a3dd-a9edac0ad71e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=551433699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.551433699
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3910901427
Short name T901
Test name
Test status
Simulation time 130207490 ps
CPU time 0.85 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 196672 kb
Host smart-a3fb99c1-aa5f-4d61-88f2-f4c9afbe05d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910901427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3910901427
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1357833101
Short name T894
Test name
Test status
Simulation time 156832713 ps
CPU time 0.91 seconds
Started Jun 09 12:33:14 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 195532 kb
Host smart-65b946b5-a30a-4acd-8412-147196abe004
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1357833101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1357833101
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093764782
Short name T860
Test name
Test status
Simulation time 273576840 ps
CPU time 1.18 seconds
Started Jun 09 12:33:15 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 196700 kb
Host smart-83160162-4c44-4e46-a558-2e9cf517ef28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093764782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3093764782
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1496664716
Short name T921
Test name
Test status
Simulation time 279793590 ps
CPU time 1.16 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 196764 kb
Host smart-c26fd173-427d-462f-94b6-f9f6bd774c91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1496664716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1496664716
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482188308
Short name T868
Test name
Test status
Simulation time 228581111 ps
CPU time 1.09 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 196784 kb
Host smart-e513dc92-4b9f-4333-8a03-d4ca17a91fc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482188308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2482188308
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2080426389
Short name T898
Test name
Test status
Simulation time 120121454 ps
CPU time 0.98 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:14 PM PDT 24
Peak memory 196572 kb
Host smart-4e9d26d9-b8c9-4b93-b52c-739b6a30c5f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2080426389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2080426389
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.239716654
Short name T934
Test name
Test status
Simulation time 783450862 ps
CPU time 0.95 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 197636 kb
Host smart-e4a3c30d-7306-47ce-aece-9bc6eee2b7ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239716654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.239716654
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.219490479
Short name T914
Test name
Test status
Simulation time 40249020 ps
CPU time 1.03 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 197764 kb
Host smart-4ec94e31-b819-4180-8ff6-debf28652770
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=219490479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.219490479
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3770111764
Short name T878
Test name
Test status
Simulation time 53644575 ps
CPU time 1.05 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 198200 kb
Host smart-9219f057-95d1-4297-a8dd-c448cf5c3c54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770111764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3770111764
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1319475560
Short name T909
Test name
Test status
Simulation time 256289584 ps
CPU time 1.13 seconds
Started Jun 09 12:33:22 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 198184 kb
Host smart-d23733f0-5181-4183-a1aa-4fb093ae509b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1319475560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1319475560
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3678374493
Short name T927
Test name
Test status
Simulation time 407810753 ps
CPU time 1.38 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 198192 kb
Host smart-308dd385-f599-4163-aade-acf15d1fa55c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678374493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3678374493
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1786999411
Short name T905
Test name
Test status
Simulation time 275191527 ps
CPU time 1.28 seconds
Started Jun 09 12:33:19 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 198064 kb
Host smart-750a5ed9-c0c8-4bcd-a102-393d328c837e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1786999411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1786999411
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3289323991
Short name T858
Test name
Test status
Simulation time 87404715 ps
CPU time 1.2 seconds
Started Jun 09 12:33:09 PM PDT 24
Finished Jun 09 12:33:10 PM PDT 24
Peak memory 196868 kb
Host smart-3b3b39a8-bd04-476b-a4bb-912be5894c2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289323991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3289323991
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1677371632
Short name T854
Test name
Test status
Simulation time 178535848 ps
CPU time 0.91 seconds
Started Jun 09 12:33:05 PM PDT 24
Finished Jun 09 12:33:06 PM PDT 24
Peak memory 196808 kb
Host smart-e26dba5b-ccdd-4285-a825-33f35265c4f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1677371632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1677371632
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1889090880
Short name T940
Test name
Test status
Simulation time 244176310 ps
CPU time 1.17 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 196688 kb
Host smart-392c27a1-b978-4937-bca9-4a81db621402
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889090880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1889090880
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1621514798
Short name T852
Test name
Test status
Simulation time 316935867 ps
CPU time 1.32 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:16 PM PDT 24
Peak memory 196068 kb
Host smart-50c95ad5-4037-4e63-8050-42680839bbd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1621514798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1621514798
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1479440360
Short name T936
Test name
Test status
Simulation time 42860692 ps
CPU time 0.84 seconds
Started Jun 09 12:33:21 PM PDT 24
Finished Jun 09 12:33:27 PM PDT 24
Peak memory 195612 kb
Host smart-1c610f4f-89c7-4eef-8a0e-5f799b9d0351
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479440360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1479440360
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.744394270
Short name T857
Test name
Test status
Simulation time 64656563 ps
CPU time 1.12 seconds
Started Jun 09 12:33:19 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196596 kb
Host smart-a4ddd2a4-bb36-49c8-9080-ca15eae50aad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=744394270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.744394270
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4158899535
Short name T847
Test name
Test status
Simulation time 175715771 ps
CPU time 0.99 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 198020 kb
Host smart-e2114651-64c4-4828-8e20-c6d859fbfed9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158899535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4158899535
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2137731490
Short name T929
Test name
Test status
Simulation time 156706220 ps
CPU time 0.94 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 195532 kb
Host smart-1fe0b49b-5522-42c2-974e-48b1beb47b24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2137731490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2137731490
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2694850193
Short name T937
Test name
Test status
Simulation time 1089684269 ps
CPU time 1.06 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 196772 kb
Host smart-816ef924-8822-4321-a5f4-6904693922e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694850193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2694850193
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.592255766
Short name T913
Test name
Test status
Simulation time 52977833 ps
CPU time 1.01 seconds
Started Jun 09 12:33:24 PM PDT 24
Finished Jun 09 12:33:25 PM PDT 24
Peak memory 196600 kb
Host smart-83db41fa-bf52-4102-be91-2362499e0931
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=592255766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.592255766
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907945489
Short name T844
Test name
Test status
Simulation time 44604291 ps
CPU time 1 seconds
Started Jun 09 12:33:09 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 196072 kb
Host smart-8f784aad-1839-4cc3-84e7-1619e7dc69ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907945489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3907945489
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1690420996
Short name T890
Test name
Test status
Simulation time 70908220 ps
CPU time 1.43 seconds
Started Jun 09 12:33:36 PM PDT 24
Finished Jun 09 12:33:38 PM PDT 24
Peak memory 198176 kb
Host smart-0dd27d48-7e81-4607-9906-2a9ea5dd2ad2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1690420996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1690420996
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618679706
Short name T869
Test name
Test status
Simulation time 94847579 ps
CPU time 0.89 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:32 PM PDT 24
Peak memory 196372 kb
Host smart-399a296e-9541-4d11-83df-36846c2fe616
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618679706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1618679706
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2984218275
Short name T928
Test name
Test status
Simulation time 242603588 ps
CPU time 1.35 seconds
Started Jun 09 12:33:21 PM PDT 24
Finished Jun 09 12:33:23 PM PDT 24
Peak memory 196648 kb
Host smart-33f60017-c131-4538-88f6-ec80039af68c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2984218275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2984218275
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3106533173
Short name T889
Test name
Test status
Simulation time 157790841 ps
CPU time 0.99 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 196568 kb
Host smart-cddc7ce6-ce4c-48b7-a858-1365b4f78773
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106533173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3106533173
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.312807564
Short name T856
Test name
Test status
Simulation time 447509905 ps
CPU time 0.94 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:24 PM PDT 24
Peak memory 196740 kb
Host smart-d92ce851-562e-4faf-b8bc-aaa1cd154667
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=312807564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.312807564
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4117333758
Short name T919
Test name
Test status
Simulation time 27500689 ps
CPU time 0.8 seconds
Started Jun 09 12:33:17 PM PDT 24
Finished Jun 09 12:33:19 PM PDT 24
Peak memory 195596 kb
Host smart-13b90c28-7b84-4e36-bc72-49ccf7557dbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117333758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4117333758
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3871959655
Short name T895
Test name
Test status
Simulation time 54992288 ps
CPU time 1.12 seconds
Started Jun 09 12:33:25 PM PDT 24
Finished Jun 09 12:33:26 PM PDT 24
Peak memory 196020 kb
Host smart-b06873ac-95b8-46b2-8dde-9f9cfdfeb702
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3871959655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3871959655
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2347329422
Short name T892
Test name
Test status
Simulation time 174836540 ps
CPU time 0.99 seconds
Started Jun 09 12:33:30 PM PDT 24
Finished Jun 09 12:33:31 PM PDT 24
Peak memory 195924 kb
Host smart-70d391c1-07ac-40c4-ab8e-75a4247b497a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347329422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2347329422
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3140031282
Short name T872
Test name
Test status
Simulation time 103336679 ps
CPU time 1.05 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196768 kb
Host smart-c4f98608-a619-4763-a817-dd74d6932382
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3140031282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3140031282
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2648129803
Short name T846
Test name
Test status
Simulation time 48868951 ps
CPU time 1.24 seconds
Started Jun 09 12:33:33 PM PDT 24
Finished Jun 09 12:33:34 PM PDT 24
Peak memory 196976 kb
Host smart-aaa79767-8203-435b-95cb-c0551ea0e7c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648129803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2648129803
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.689471347
Short name T912
Test name
Test status
Simulation time 114521348 ps
CPU time 0.79 seconds
Started Jun 09 12:33:20 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 195504 kb
Host smart-d1d3165a-9f95-4609-80d1-2f290b1e56a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=689471347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.689471347
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.124855474
Short name T933
Test name
Test status
Simulation time 43580645 ps
CPU time 1.23 seconds
Started Jun 09 12:33:16 PM PDT 24
Finished Jun 09 12:33:18 PM PDT 24
Peak memory 198208 kb
Host smart-ba200ec6-0f8b-4292-8166-a6df153fd608
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124855474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.124855474
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2241569555
Short name T880
Test name
Test status
Simulation time 51672179 ps
CPU time 1.09 seconds
Started Jun 09 12:33:09 PM PDT 24
Finished Jun 09 12:33:11 PM PDT 24
Peak memory 198156 kb
Host smart-2c96f796-787a-4968-a6e9-e083881ba68c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2241569555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2241569555
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3574442713
Short name T881
Test name
Test status
Simulation time 61796596 ps
CPU time 1.11 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 195884 kb
Host smart-533d2b51-57be-42c6-8d90-6ae5fcf27a05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574442713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3574442713
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3314768757
Short name T863
Test name
Test status
Simulation time 48361521 ps
CPU time 0.95 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 195580 kb
Host smart-4604bf74-ee0a-4498-af8c-9e1f63927fd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3314768757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3314768757
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.647131951
Short name T884
Test name
Test status
Simulation time 349066938 ps
CPU time 1.32 seconds
Started Jun 09 12:33:18 PM PDT 24
Finished Jun 09 12:33:20 PM PDT 24
Peak memory 196872 kb
Host smart-958907f5-1601-4a67-abab-6e5ab50071f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647131951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.647131951
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4110543121
Short name T879
Test name
Test status
Simulation time 296245295 ps
CPU time 1.28 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 195656 kb
Host smart-db38f156-6339-46f8-a85f-36320843ef1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4110543121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4110543121
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1334211725
Short name T850
Test name
Test status
Simulation time 53394361 ps
CPU time 0.95 seconds
Started Jun 09 12:33:11 PM PDT 24
Finished Jun 09 12:33:12 PM PDT 24
Peak memory 196760 kb
Host smart-fc558579-ab36-4012-84ba-f59f4c2fb448
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334211725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1334211725
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3062058204
Short name T907
Test name
Test status
Simulation time 119671212 ps
CPU time 0.83 seconds
Started Jun 09 12:33:11 PM PDT 24
Finished Jun 09 12:33:13 PM PDT 24
Peak memory 195524 kb
Host smart-93b01097-ef3c-483c-8bea-88a9d2d2e875
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3062058204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3062058204
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1631891055
Short name T915
Test name
Test status
Simulation time 54083619 ps
CPU time 1.04 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 196584 kb
Host smart-177c73e7-a74c-4216-8a5c-4dd9299b8f6a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631891055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1631891055
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3337993786
Short name T897
Test name
Test status
Simulation time 61401847 ps
CPU time 0.97 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 197376 kb
Host smart-0339aba5-7c8e-4f64-9e05-8e064b37022a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3337993786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3337993786
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2337248455
Short name T939
Test name
Test status
Simulation time 232856014 ps
CPU time 1.14 seconds
Started Jun 09 12:33:13 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 196688 kb
Host smart-a77f97ce-5ff6-435f-8ef4-2a2c7658200c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337248455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2337248455
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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