Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4634874	1			T19	1		T20	863		T21	54865
all_pins[1]	4634874	1			T19	1		T20	863		T21	54865
all_pins[2]	4634874	1			T19	1		T20	863		T21	54865
all_pins[3]	4634874	1			T19	1		T20	863		T21	54865
all_pins[4]	4634874	1			T19	1		T20	863		T21	54865
all_pins[5]	4634874	1			T19	1		T20	863		T21	54865
all_pins[6]	4634874	1			T19	1		T20	863		T21	54865
all_pins[7]	4634874	1			T19	1		T20	863		T21	54865
all_pins[8]	4634874	1			T19	1		T20	863		T21	54865
all_pins[9]	4634874	1			T19	1		T20	863		T21	54865
all_pins[10]	4634874	1			T19	1		T20	863		T21	54865
all_pins[11]	4634874	1			T19	1		T20	863		T21	54865
all_pins[12]	4634874	1			T19	1		T20	863		T21	54865
all_pins[13]	4634874	1			T19	1		T20	863		T21	54865
all_pins[14]	4634874	1			T19	1		T20	863		T21	54865
all_pins[15]	4634874	1			T19	1		T20	863		T21	54865
all_pins[16]	4634874	1			T19	1		T20	863		T21	54865
all_pins[17]	4634874	1			T19	1		T20	863		T21	54865
all_pins[18]	4634874	1			T19	1		T20	863		T21	54865
all_pins[19]	4634874	1			T19	1		T20	863		T21	54865
all_pins[20]	4634874	1			T19	1		T20	863		T21	54865
all_pins[21]	4634874	1			T19	1		T20	863		T21	54865
all_pins[22]	4634874	1			T19	1		T20	863		T21	54865
all_pins[23]	4634874	1			T19	1		T20	863		T21	54865
all_pins[24]	4634874	1			T19	1		T20	863		T21	54865
all_pins[25]	4634874	1			T19	1		T20	863		T21	54865
all_pins[26]	4634874	1			T19	1		T20	863		T21	54865
all_pins[27]	4634874	1			T19	1		T20	863		T21	54865
all_pins[28]	4634874	1			T19	1		T20	863		T21	54865
all_pins[29]	4634874	1			T19	1		T20	863		T21	54865
all_pins[30]	4634874	1			T19	1		T20	863		T21	54865
all_pins[31]	4634874	1			T19	1		T20	863		T21	54865

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	92147533	1			T19	32		T20	17267		T21	109714
values[0x1]	56168435	1			T20	10349		T21	658537		T22	1341
transitions[0x0=>0x1]	33675259	1			T20	6163		T21	397922		T22	690
transitions[0x1=>0x0]	33675106	1			T20	6163		T21	397922		T22	689

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2880739	1			T19	1		T20	561		T21	34069
all_pins[0]	values[0x1]	1754135	1			T20	302		T21	20796		T22	41
all_pins[0]	transitions[0x0=>0x1]	1086849	1			T20	180		T21	12772		T22	21
all_pins[0]	transitions[0x1=>0x0]	1086802	1			T20	180		T21	12774		T22	18
all_pins[1]	values[0x0]	2878427	1			T19	1		T20	547		T21	33802
all_pins[1]	values[0x1]	1756447	1			T20	316		T21	21063		T22	52
all_pins[1]	transitions[0x0=>0x1]	1051889	1			T20	231		T21	12446		T22	30
all_pins[1]	transitions[0x1=>0x0]	1049577	1			T20	217		T21	12179		T22	19
all_pins[2]	values[0x0]	2882298	1			T19	1		T20	541		T21	33878
all_pins[2]	values[0x1]	1752576	1			T20	322		T21	20987		T22	45
all_pins[2]	transitions[0x0=>0x1]	1049578	1			T20	193		T21	12381		T22	20
all_pins[2]	transitions[0x1=>0x0]	1053449	1			T20	187		T21	12457		T22	27
all_pins[3]	values[0x0]	2882416	1			T19	1		T20	551		T21	34217
all_pins[3]	values[0x1]	1752458	1			T20	312		T21	20648		T22	39
all_pins[3]	transitions[0x0=>0x1]	1050288	1			T20	173		T21	12551		T22	18
all_pins[3]	transitions[0x1=>0x0]	1050406	1			T20	183		T21	12890		T22	24
all_pins[4]	values[0x0]	2875619	1			T19	1		T20	479		T21	34652
all_pins[4]	values[0x1]	1759255	1			T20	384		T21	20213		T22	44
all_pins[4]	transitions[0x0=>0x1]	1053747	1			T20	242		T21	11965		T22	20
all_pins[4]	transitions[0x1=>0x0]	1046950	1			T20	170		T21	12400		T22	15
all_pins[5]	values[0x0]	2882060	1			T19	1		T20	569		T21	34157
all_pins[5]	values[0x1]	1752814	1			T20	294		T21	20708		T22	42
all_pins[5]	transitions[0x0=>0x1]	1047084	1			T20	147		T21	12939		T22	22
all_pins[5]	transitions[0x1=>0x0]	1053525	1			T20	237		T21	12444		T22	24
all_pins[6]	values[0x0]	2879955	1			T19	1		T20	550		T21	34659
all_pins[6]	values[0x1]	1754919	1			T20	313		T21	20206		T22	35
all_pins[6]	transitions[0x0=>0x1]	1051983	1			T20	165		T21	11980		T22	16
all_pins[6]	transitions[0x1=>0x0]	1049878	1			T20	146		T21	12482		T22	23
all_pins[7]	values[0x0]	2879199	1			T19	1		T20	545		T21	34572
all_pins[7]	values[0x1]	1755675	1			T20	318		T21	20293		T22	41
all_pins[7]	transitions[0x0=>0x1]	1052856	1			T20	176		T21	12426		T22	23
all_pins[7]	transitions[0x1=>0x0]	1052100	1			T20	171		T21	12339		T22	17
all_pins[8]	values[0x0]	2883006	1			T19	1		T20	513		T21	34549
all_pins[8]	values[0x1]	1751868	1			T20	350		T21	20316		T22	40
all_pins[8]	transitions[0x0=>0x1]	1049925	1			T20	221		T21	12365		T22	20
all_pins[8]	transitions[0x1=>0x0]	1053732	1			T20	189		T21	12342		T22	21
all_pins[9]	values[0x0]	2883977	1			T19	1		T20	550		T21	34044
all_pins[9]	values[0x1]	1750897	1			T20	313		T21	20821		T22	46
all_pins[9]	transitions[0x0=>0x1]	1047512	1			T20	195		T21	12250		T22	23
all_pins[9]	transitions[0x1=>0x0]	1048483	1			T20	232		T21	11745		T22	17
all_pins[10]	values[0x0]	2879068	1			T19	1		T20	555		T21	33756
all_pins[10]	values[0x1]	1755806	1			T20	308		T21	21109		T22	42
all_pins[10]	transitions[0x0=>0x1]	1051812	1			T20	181		T21	12526		T22	14
all_pins[10]	transitions[0x1=>0x0]	1046903	1			T20	186		T21	12238		T22	18
all_pins[11]	values[0x0]	2875641	1			T19	1		T20	581		T21	34272
all_pins[11]	values[0x1]	1759233	1			T20	282		T21	20593		T22	39
all_pins[11]	transitions[0x0=>0x1]	1053507	1			T20	169		T21	12287		T22	20
all_pins[11]	transitions[0x1=>0x0]	1050080	1			T20	195		T21	12803		T22	23
all_pins[12]	values[0x0]	2885667	1			T19	1		T20	547		T21	34346
all_pins[12]	values[0x1]	1749207	1			T20	316		T21	20519		T22	42
all_pins[12]	transitions[0x0=>0x1]	1045245	1			T20	204		T21	12233		T22	22
all_pins[12]	transitions[0x1=>0x0]	1055271	1			T20	170		T21	12307		T22	19
all_pins[13]	values[0x0]	2877761	1			T19	1		T20	557		T21	33960
all_pins[13]	values[0x1]	1757113	1			T20	306		T21	20905		T22	47
all_pins[13]	transitions[0x0=>0x1]	1055548	1			T20	172		T21	12656		T22	29
all_pins[13]	transitions[0x1=>0x0]	1047642	1			T20	182		T21	12270		T22	24
all_pins[14]	values[0x0]	2879459	1			T19	1		T20	558		T21	34018
all_pins[14]	values[0x1]	1755415	1			T20	305		T21	20847		T22	45
all_pins[14]	transitions[0x0=>0x1]	1051510	1			T20	194		T21	12731		T22	24
all_pins[14]	transitions[0x1=>0x0]	1053208	1			T20	195		T21	12789		T22	26
all_pins[15]	values[0x0]	2880923	1			T19	1		T20	533		T21	34122
all_pins[15]	values[0x1]	1753951	1			T20	330		T21	20743		T22	47
all_pins[15]	transitions[0x0=>0x1]	1052088	1			T20	203		T21	12538		T22	26
all_pins[15]	transitions[0x1=>0x0]	1053552	1			T20	178		T21	12642		T22	24
all_pins[16]	values[0x0]	2885512	1			T19	1		T20	507		T21	34723
all_pins[16]	values[0x1]	1749362	1			T20	356		T21	20142		T22	43
all_pins[16]	transitions[0x0=>0x1]	1049128	1			T20	208		T21	12339		T22	19
all_pins[16]	transitions[0x1=>0x0]	1053717	1			T20	182		T21	12940		T22	23
all_pins[17]	values[0x0]	2881903	1			T19	1		T20	486		T21	34657
all_pins[17]	values[0x1]	1752971	1			T20	377		T21	20208		T22	41
all_pins[17]	transitions[0x0=>0x1]	1054523	1			T20	225		T21	12562		T22	20
all_pins[17]	transitions[0x1=>0x0]	1050914	1			T20	204		T21	12496		T22	22
all_pins[18]	values[0x0]	2878652	1			T19	1		T20	595		T21	33880
all_pins[18]	values[0x1]	1756222	1			T20	268		T21	20985		T22	38
all_pins[18]	transitions[0x0=>0x1]	1051611	1			T20	175		T21	12814		T22	20
all_pins[18]	transitions[0x1=>0x0]	1048360	1			T20	284		T21	12037		T22	23
all_pins[19]	values[0x0]	2881300	1			T19	1		T20	547		T21	34428
all_pins[19]	values[0x1]	1753574	1			T20	316		T21	20437		T22	47
all_pins[19]	transitions[0x0=>0x1]	1047310	1			T20	223		T21	12251		T22	26
all_pins[19]	transitions[0x1=>0x0]	1049958	1			T20	175		T21	12799		T22	17
all_pins[20]	values[0x0]	2876276	1			T19	1		T20	517		T21	34369
all_pins[20]	values[0x1]	1758598	1			T20	346		T21	20496		T22	42
all_pins[20]	transitions[0x0=>0x1]	1055011	1			T20	232		T21	12289		T22	15
all_pins[20]	transitions[0x1=>0x0]	1049987	1			T20	202		T21	12230		T22	20
all_pins[21]	values[0x0]	2880392	1			T19	1		T20	519		T21	33927
all_pins[21]	values[0x1]	1754482	1			T20	344		T21	20938		T22	45
all_pins[21]	transitions[0x0=>0x1]	1048446	1			T20	193		T21	12853		T22	23
all_pins[21]	transitions[0x1=>0x0]	1052562	1			T20	195		T21	12411		T22	20
all_pins[22]	values[0x0]	2872728	1			T19	1		T20	524		T21	35091
all_pins[22]	values[0x1]	1762146	1			T20	339		T21	19774		T22	46
all_pins[22]	transitions[0x0=>0x1]	1057085	1			T20	192		T21	11611		T22	24
all_pins[22]	transitions[0x1=>0x0]	1049421	1			T20	197		T21	12775		T22	23
all_pins[23]	values[0x0]	2884174	1			T19	1		T20	542		T21	34238
all_pins[23]	values[0x1]	1750700	1			T20	321		T21	20627		T22	48
all_pins[23]	transitions[0x0=>0x1]	1044638	1			T20	175		T21	12740		T22	21
all_pins[23]	transitions[0x1=>0x0]	1056084	1			T20	193		T21	11887		T22	19
all_pins[24]	values[0x0]	2880889	1			T19	1		T20	521		T21	34299
all_pins[24]	values[0x1]	1753985	1			T20	342		T21	20566		T22	38
all_pins[24]	transitions[0x0=>0x1]	1052224	1			T20	179		T21	12557		T22	13
all_pins[24]	transitions[0x1=>0x0]	1048939	1			T20	158		T21	12618		T22	23
all_pins[25]	values[0x0]	2882615	1			T19	1		T20	552		T21	34149
all_pins[25]	values[0x1]	1752259	1			T20	311		T21	20716		T22	34
all_pins[25]	transitions[0x0=>0x1]	1051591	1			T20	151		T21	12589		T22	18
all_pins[25]	transitions[0x1=>0x0]	1053317	1			T20	182		T21	12439		T22	22
all_pins[26]	values[0x0]	2876921	1			T19	1		T20	565		T21	34922
all_pins[26]	values[0x1]	1757953	1			T20	298		T21	19943		T22	34
all_pins[26]	transitions[0x0=>0x1]	1054305	1			T20	185		T21	12083		T22	21
all_pins[26]	transitions[0x1=>0x0]	1048611	1			T20	198		T21	12856		T22	21
all_pins[27]	values[0x0]	2877127	1			T19	1		T20	522		T21	34041
all_pins[27]	values[0x1]	1757747	1			T20	341		T21	20824		T22	26
all_pins[27]	transitions[0x0=>0x1]	1052500	1			T20	215		T21	12786		T22	20
all_pins[27]	transitions[0x1=>0x0]	1052706	1			T20	172		T21	11905		T22	28
all_pins[28]	values[0x0]	2871089	1			T19	1		T20	551		T21	35022
all_pins[28]	values[0x1]	1763785	1			T20	312		T21	19843		T22	46
all_pins[28]	transitions[0x0=>0x1]	1055090	1			T20	184		T21	11756		T22	34
all_pins[28]	transitions[0x1=>0x0]	1049052	1			T20	213		T21	12737		T22	14
all_pins[29]	values[0x0]	2874904	1			T19	1		T20	466		T21	33993
all_pins[29]	values[0x1]	1759970	1			T20	397		T21	20872		T22	42
all_pins[29]	transitions[0x0=>0x1]	1050009	1			T20	239		T21	12949		T22	23
all_pins[29]	transitions[0x1=>0x0]	1053824	1			T20	154		T21	11920		T22	27
all_pins[30]	values[0x0]	2876203	1			T19	1		T20	555		T21	34264
all_pins[30]	values[0x1]	1758671	1			T20	308		T21	20601		T22	45
all_pins[30]	transitions[0x0=>0x1]	1049441	1			T20	154		T21	12273		T22	24
all_pins[30]	transitions[0x1=>0x0]	1050740	1			T20	243		T21	12544		T22	21
all_pins[31]	values[0x0]	2880633	1			T19	1		T20	561		T21	34067
all_pins[31]	values[0x1]	1754241	1			T20	302		T21	20798		T22	39
all_pins[31]	transitions[0x0=>0x1]	1050926	1			T20	187		T21	12424		T22	21
all_pins[31]	transitions[0x1=>0x0]	1055356	1			T20	193		T21	12227		T22	27