Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[1]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[2]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[3]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[4]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[5]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[6]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[7]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[8]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[9]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[10]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[11]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[12]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[13]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[14]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[15]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[16]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[17]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[18]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[19]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[20]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[21]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[22]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[23]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[24]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[25]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[26]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[27]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[28]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[29]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[30]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[31]	15283231	1			T19	472		T20	2156		T21	157903

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295750539

1

T19

3651

T20

15971

T21

340499

auto[1]

193312853

1

T19

11453

T20

53021

T21

164790

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392498494

1

T19

11264

T20

40685

T21

373077

auto[1]

96564898

1

T19

3840

T20

28307

T21

132211

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

364121482

1

T19

7607

T20

34859

T21

342500

auto[1]

124941910

1

T19

7497

T20

34133

T21

162789

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5734598	1			T19	35		T20	15		T21	56231
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4120968	1			T19	160		T20	596		T21	28961
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1519477	1			T19	45		T20	497		T21	20246
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1984151	1			T19	21		T20	37		T21	29006
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	415836	1			T19	176		T20	537		T21	1814
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1508201	1			T19	35		T20	474		T21	21645
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5742712	1			T19	34		T20	32		T21	56865
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4120786	1			T19	166		T20	695		T21	29409
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1519888	1			T19	58		T20	472		T21	21190
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1980891	1			T19	32		T20	19		T21	28828
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	415799	1			T19	125		T20	579		T21	1710
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1503155	1			T19	57		T20	359		T21	19901
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5740125	1			T19	44		T20	19		T21	57804
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4118623	1			T19	153		T20	557		T21	29165
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1514214	1			T19	53		T20	407		T21	21074
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1987905	1			T19	18		T20	30		T21	28234
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	413945	1			T19	157		T20	601		T21	1596
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1508419	1			T19	47		T20	542		T21	20030
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5723240	1			T19	23		T20	27		T21	56366
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4126461	1			T19	132		T20	691		T21	28936
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1515212	1			T19	45		T20	474		T21	20085
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1989733	1			T19	23		T20	39		T21	29698
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	418198	1			T19	187		T20	593		T21	1832
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1510387	1			T19	62		T20	332		T21	20986
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5744375	1			T19	21		T20	46		T21	57216
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4120603	1			T19	115		T20	630		T21	29124
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1516317	1			T19	91		T20	573		T21	20148
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1982879	1			T19	26		T20	20		T21	29187
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	415261	1			T19	143		T20	535		T21	1735
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1503796	1			T19	76		T20	352		T21	20493
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5736761	1			T19	38		T20	20		T21	56179
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4122322	1			T19	158		T20	617		T21	29390
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1517593	1			T19	68		T20	488		T21	21693
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1984955	1			T19	22		T20	39		T21	28365
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	417520	1			T19	104		T20	547		T21	1775
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1504080	1			T19	82		T20	445		T21	20501
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5733047	1			T19	18		T20	22		T21	57200
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4122247	1			T19	135		T20	548		T21	29111
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1522478	1			T19	73		T20	389		T21	20956
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1985336	1			T19	29		T20	23		T21	28191
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	416379	1			T19	157		T20	617		T21	1712
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1503744	1			T19	60		T20	557		T21	20733
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5740173	1			T19	38		T20	32		T21	57600
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4119002	1			T19	180		T20	558		T21	29122
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1520399	1			T19	121		T20	417		T21	20539
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1981396	1			T19	7		T20	21		T21	28271
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	413576	1			T19	82		T20	633		T21	1683
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1508685	1			T19	44		T20	495		T21	20688
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5741557	1			T19	16		T20	50		T21	57590
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4119889	1			T19	121		T20	661		T21	29222
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1515606	1			T19	92		T20	422		T21	21489
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1984180	1			T19	34		T20	17		T21	27626
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	416417	1			T19	143		T20	659		T21	1570
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1505582	1			T19	66		T20	347		T21	20406
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5738691	1			T19	16		T20	37		T21	56681
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4124890	1			T19	128		T20	679		T21	29517
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1514182	1			T19	66		T20	412		T21	20679
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1990243	1			T19	33		T20	16		T21	28619
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	414068	1			T19	138		T20	600		T21	1803
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1501157	1			T19	91		T20	412		T21	20604
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5733146	1			T19	18		T20	22		T21	57019
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4130758	1			T19	93		T20	609		T21	29344
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1515261	1			T19	64		T20	511		T21	20992
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1983618	1			T19	31		T20	30		T21	28011
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	416246	1			T19	160		T20	581		T21	1636
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1504202	1			T19	106		T20	403		T21	20901
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5737483	1			T19	35		T20	24		T21	56840
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4119584	1			T19	192		T20	686		T21	29443
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1518634	1			T19	53		T20	330		T21	20540
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1980883	1			T19	22		T20	19		T21	28611
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	415001	1			T19	125		T20	623		T21	1662
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1511646	1			T19	45		T20	474		T21	20807
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5731869	1			T19	24		T20	22		T21	56949
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4125034	1			T19	208		T20	507		T21	29406
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1515748	1			T19	45		T20	501		T21	20775
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1987078	1			T19	32		T20	33		T21	28302
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	416174	1			T19	141		T20	584		T21	1799
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1507328	1			T19	22		T20	509		T21	20672
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5723091	1			T19	13		T20	32		T21	56462
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4133566	1			T19	102		T20	697		T21	29014
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1519327	1			T19	51		T20	361		T21	20385
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1985814	1			T19	34		T20	22		T21	29163
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	418788	1			T19	213		T20	605		T21	1820
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1502645	1			T19	59		T20	439		T21	21059
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5734826	1			T19	9		T20	44		T21	56964
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4123117	1			T19	137		T20	532		T21	29072
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1514670	1			T19	71		T20	481		T21	21022
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1991119	1			T19	22		T20	22		T21	28434
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	414866	1			T19	165		T20	666		T21	1785
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1504633	1			T19	68		T20	411		T21	20626
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5752477	1			T19	25		T20	14		T21	57406
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4117775	1			T19	206		T20	446		T21	29474
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1519265	1			T19	24		T20	509		T21	20919
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1976198	1			T19	17		T20	53		T21	28159
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	415094	1			T19	153		T20	675		T21	1649
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1502422	1			T19	47		T20	459		T21	20296
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5738082	1			T19	23		T20	25		T21	56653
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4124601	1			T19	157		T20	713		T21	29183
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1510944	1			T19	69		T20	451		T21	20369
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1993476	1			T19	20		T20	22		T21	29554
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	417288	1			T19	176		T20	600		T21	1726
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1498840	1			T19	27		T20	345		T21	20418
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5742798	1			T19	32		T20	27		T21	56911
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4120567	1			T19	227		T20	653		T21	29337
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1515953	1			T19	61		T20	455		T21	21470
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1988497	1			T19	14		T20	25		T21	28478
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	416408	1			T19	102		T20	560		T21	1677
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1499008	1			T19	36		T20	436		T21	20030
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5742624	1			T19	28		T20	29		T21	56640
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4132068	1			T19	167		T20	670		T21	29213
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1516045	1			T19	73		T20	355		T21	20786
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1983235	1			T19	15		T20	29		T21	28872
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	417458	1			T19	131		T20	646		T21	1617
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1491801	1			T19	58		T20	427		T21	20775
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5744826	1			T19	22		T20	32		T21	57677
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4120040	1			T19	158		T20	669		T21	29219
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1511237	1			T19	52		T20	281		T21	20632
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1987861	1			T19	23		T20	22		T21	28643
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	419005	1			T19	141		T20	640		T21	1680
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1500262	1			T19	76		T20	512		T21	20052
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5740699	1			T19	36		T20	29		T21	57555
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4126784	1			T19	177		T20	567		T21	29317
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1513820	1			T19	73		T20	472		T21	20751
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1985852	1			T19	28		T20	17		T21	28222
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	415462	1			T19	119		T20	513		T21	1613
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1500614	1			T19	39		T20	558		T21	20445
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5755284	1			T19	22		T20	13		T21	57619
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4105061	1			T19	137		T20	573		T21	29192
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1511435	1			T19	39		T20	424		T21	20909
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1991363	1			T19	29		T20	37		T21	28714
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	419871	1			T19	148		T20	642		T21	1564
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1500217	1			T19	97		T20	467		T21	19905
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5747097	1			T19	18		T20	36		T21	56140
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4122013	1			T19	160		T20	673		T21	29394
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1517597	1			T19	36		T20	423		T21	20744
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1979417	1			T19	31		T20	28		T21	29203
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	417514	1			T19	169		T20	602		T21	1804
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1499593	1			T19	58		T20	394		T21	20618
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5744374	1			T19	35		T20	38		T21	56567
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4120188	1			T19	159		T20	666		T21	29320
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1513480	1			T19	25		T20	399		T21	21180
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1988158	1			T19	31		T20	24		T21	28856
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	416507	1			T19	170		T20	651		T21	1756
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1500524	1			T19	52		T20	378		T21	20224
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5744114	1			T19	35		T20	19		T21	56184
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4116317	1			T19	152		T20	654		T21	29563
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1514453	1			T19	62		T20	482		T21	20788
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1991340	1			T19	30		T20	32		T21	29054
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	416468	1			T19	133		T20	592		T21	1811
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1500539	1			T19	60		T20	377		T21	20503
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5742638	1			T19	16		T20	34		T21	56414
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4125376	1			T19	128		T20	650		T21	29386
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1513844	1			T19	59		T20	348		T21	21255
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1991722	1			T19	34		T20	14		T21	28147
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	415341	1			T19	183		T20	678		T21	1697
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1494310	1			T19	52		T20	432		T21	21004
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5734033	1			T19	40		T20	26		T21	56711
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4124408	1			T19	157		T20	467		T21	29020
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1509590	1			T19	63		T20	451		T21	20552
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1995084	1			T19	30		T20	26		T21	29221
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	416062	1			T19	135		T20	631		T21	1860
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1504054	1			T19	47		T20	555		T21	20539
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5754375	1			T19	18		T20	28		T21	56785
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4116787	1			T19	129		T20	685		T21	29435
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1521261	1			T19	67		T20	434		T21	20588
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1984540	1			T19	45		T20	25		T21	28913
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	413220	1			T19	174		T20	515		T21	1737
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1493048	1			T19	39		T20	469		T21	20445
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5739773	1			T19	20		T20	27		T21	57753
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4124309	1			T19	102		T20	700		T21	29355
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1517739	1			T19	87		T20	496		T21	20851
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1984642	1			T19	29		T20	26		T21	28135
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	418415	1			T19	159		T20	536		T21	1579
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1498353	1			T19	75		T20	371		T21	20230
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5748459	1			T19	27		T20	15		T21	57200
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4123784	1			T19	165		T20	517		T21	29385
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1514340	1			T19	59		T20	557		T21	20368
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1985241	1			T19	24		T20	42		T21	28723
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	416631	1			T19	148		T20	526		T21	1770
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1494776	1			T19	49		T20	499		T21	20457
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5742649	1			T19	30		T20	32		T21	57265
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4128824	1			T19	117		T20	532		T21	29211
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1514252	1			T19	58		T20	550		T21	20936
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1983972	1			T19	35		T20	22		T21	28633
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	418082	1			T19	158		T20	580		T21	1759
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1495452	1			T19	74		T20	440		T21	20099
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5736737	1			T19	26		T20	26		T21	57457
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4132713	1			T19	119		T20	644		T21	29297
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1511023	1			T19	72		T20	401		T21	20652
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1987743	1			T19	20		T20	23		T21	28457
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	416874	1			T19	176		T20	648		T21	1578
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1498141	1			T19	59		T20	414		T21	20462

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal