Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[1]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[2]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[3]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[4]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[5]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[6]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[7]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[8]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[9]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[10]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[11]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[12]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[13]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[14]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[15]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[16]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[17]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[18]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[19]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[20]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[21]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[22]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[23]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[24]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[25]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[26]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[27]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[28]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[29]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[30]	15283231	1			T19	472		T20	2156		T21	157903
bins_for_gpio_bits[31]	15283231	1			T19	472		T20	2156		T21	157903

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295750539

1

T19

3651

T20

15971

T21

340499

auto[1]

193312853

1

T19

11453

T20

53021

T21

164790

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295741298

1

T19

3657

T20

15981

T21

340498

auto[1]

193322094

1

T19

11447

T20

53011

T21

164791

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8966602	1			T19	92		T20	475		T21	101694
bins_for_gpio_bits[0]	auto[0]	auto[1]	271330	1			T19	9		T20	74		T21	3788
bins_for_gpio_bits[0]	auto[1]	auto[0]	271624	1			T19	9		T20	74		T21	3789
bins_for_gpio_bits[0]	auto[1]	auto[1]	5773675	1			T19	362		T20	1533		T21	48632
bins_for_gpio_bits[1]	auto[0]	auto[0]	8972361	1			T19	113		T20	452		T21	103265
bins_for_gpio_bits[1]	auto[0]	auto[1]	270857	1			T19	11		T20	72		T21	3618
bins_for_gpio_bits[1]	auto[1]	auto[0]	271130	1			T19	11		T20	71		T21	3618
bins_for_gpio_bits[1]	auto[1]	auto[1]	5768883	1			T19	337		T20	1561		T21	47402
bins_for_gpio_bits[2]	auto[0]	auto[0]	8970275	1			T19	106		T20	393		T21	103492
bins_for_gpio_bits[2]	auto[0]	auto[1]	271631	1			T19	9		T20	64		T21	3620
bins_for_gpio_bits[2]	auto[1]	auto[0]	271969	1			T19	9		T20	63		T21	3620
bins_for_gpio_bits[2]	auto[1]	auto[1]	5769356	1			T19	348		T20	1636		T21	47171
bins_for_gpio_bits[3]	auto[0]	auto[0]	8956217	1			T19	83		T20	476		T21	102429
bins_for_gpio_bits[3]	auto[0]	auto[1]	271695	1			T19	8		T20	64		T21	3720
bins_for_gpio_bits[3]	auto[1]	auto[0]	271968	1			T19	8		T20	64		T21	3720
bins_for_gpio_bits[3]	auto[1]	auto[1]	5783351	1			T19	373		T20	1552		T21	48034
bins_for_gpio_bits[4]	auto[0]	auto[0]	8972613	1			T19	121		T20	567		T21	102873
bins_for_gpio_bits[4]	auto[0]	auto[1]	270652	1			T19	18		T20	72		T21	3678
bins_for_gpio_bits[4]	auto[1]	auto[0]	270958	1			T19	17		T20	72		T21	3678
bins_for_gpio_bits[4]	auto[1]	auto[1]	5769008	1			T19	316		T20	1445		T21	47674
bins_for_gpio_bits[5]	auto[0]	auto[0]	8967728	1			T19	114		T20	474		T21	102543
bins_for_gpio_bits[5]	auto[0]	auto[1]	271281	1			T19	14		T20	73		T21	3693
bins_for_gpio_bits[5]	auto[1]	auto[0]	271581	1			T19	14		T20	73		T21	3694
bins_for_gpio_bits[5]	auto[1]	auto[1]	5772641	1			T19	330		T20	1536		T21	47973
bins_for_gpio_bits[6]	auto[0]	auto[0]	8968699	1			T19	108		T20	371		T21	102662
bins_for_gpio_bits[6]	auto[0]	auto[1]	271873	1			T19	12		T20	63		T21	3685
bins_for_gpio_bits[6]	auto[1]	auto[0]	272162	1			T19	12		T20	63		T21	3685
bins_for_gpio_bits[6]	auto[1]	auto[1]	5770497	1			T19	340		T20	1659		T21	47871
bins_for_gpio_bits[7]	auto[0]	auto[0]	8970126	1			T19	147		T20	405		T21	102754
bins_for_gpio_bits[7]	auto[0]	auto[1]	271560	1			T19	19		T20	65		T21	3655
bins_for_gpio_bits[7]	auto[1]	auto[0]	271842	1			T19	19		T20	65		T21	3656
bins_for_gpio_bits[7]	auto[1]	auto[1]	5769703	1			T19	287		T20	1621		T21	47838
bins_for_gpio_bits[8]	auto[0]	auto[0]	8970049	1			T19	132		T20	420		T21	103083
bins_for_gpio_bits[8]	auto[0]	auto[1]	270995	1			T19	10		T20	69		T21	3621
bins_for_gpio_bits[8]	auto[1]	auto[0]	271294	1			T19	10		T20	69		T21	3622
bins_for_gpio_bits[8]	auto[1]	auto[1]	5770893	1			T19	320		T20	1598		T21	47577
bins_for_gpio_bits[9]	auto[0]	auto[0]	8972142	1			T19	103		T20	409		T21	102309
bins_for_gpio_bits[9]	auto[0]	auto[1]	270706	1			T19	13		T20	57		T21	3670
bins_for_gpio_bits[9]	auto[1]	auto[0]	270974	1			T19	12		T20	56		T21	3670
bins_for_gpio_bits[9]	auto[1]	auto[1]	5769409	1			T19	344		T20	1634		T21	48254
bins_for_gpio_bits[10]	auto[0]	auto[0]	8960944	1			T19	98		T20	491		T21	102294
bins_for_gpio_bits[10]	auto[0]	auto[1]	270820	1			T19	15		T20	72		T21	3728
bins_for_gpio_bits[10]	auto[1]	auto[0]	271081	1			T19	15		T20	72		T21	3728
bins_for_gpio_bits[10]	auto[1]	auto[1]	5780386	1			T19	344		T20	1521		T21	48153
bins_for_gpio_bits[11]	auto[0]	auto[0]	8965036	1			T19	99		T20	321		T21	102334
bins_for_gpio_bits[11]	auto[0]	auto[1]	271663	1			T19	12		T20	52		T21	3656
bins_for_gpio_bits[11]	auto[1]	auto[0]	271964	1			T19	11		T20	52		T21	3657
bins_for_gpio_bits[11]	auto[1]	auto[1]	5774568	1			T19	350		T20	1731		T21	48256
bins_for_gpio_bits[12]	auto[0]	auto[0]	8962818	1			T19	91		T20	477		T21	102311
bins_for_gpio_bits[12]	auto[0]	auto[1]	271612	1			T19	10		T20	79		T21	3714
bins_for_gpio_bits[12]	auto[1]	auto[0]	271877	1			T19	10		T20	79		T21	3715
bins_for_gpio_bits[12]	auto[1]	auto[1]	5776924	1			T19	361		T20	1521		T21	48163
bins_for_gpio_bits[13]	auto[0]	auto[0]	8957100	1			T19	90		T20	356		T21	102270
bins_for_gpio_bits[13]	auto[0]	auto[1]	270839	1			T19	8		T20	59		T21	3740
bins_for_gpio_bits[13]	auto[1]	auto[0]	271132	1			T19	8		T20	59		T21	3740
bins_for_gpio_bits[13]	auto[1]	auto[1]	5784160	1			T19	366		T20	1682		T21	48153
bins_for_gpio_bits[14]	auto[0]	auto[0]	8969183	1			T19	88		T20	489		T21	102784
bins_for_gpio_bits[14]	auto[0]	auto[1]	271166	1			T19	15		T20	59		T21	3636
bins_for_gpio_bits[14]	auto[1]	auto[0]	271432	1			T19	14		T20	58		T21	3636
bins_for_gpio_bits[14]	auto[1]	auto[1]	5771450	1			T19	355		T20	1550		T21	47847
bins_for_gpio_bits[15]	auto[0]	auto[0]	8977189	1			T19	60		T20	507		T21	102864
bins_for_gpio_bits[15]	auto[0]	auto[1]	270455	1			T19	6		T20	70		T21	3620
bins_for_gpio_bits[15]	auto[1]	auto[0]	270751	1			T19	6		T20	69		T21	3620
bins_for_gpio_bits[15]	auto[1]	auto[1]	5764836	1			T19	400		T20	1510		T21	47799
bins_for_gpio_bits[16]	auto[0]	auto[0]	8971103	1			T19	103		T20	439		T21	102928
bins_for_gpio_bits[16]	auto[0]	auto[1]	271097	1			T19	9		T20	60		T21	3646
bins_for_gpio_bits[16]	auto[1]	auto[0]	271399	1			T19	9		T20	59		T21	3648
bins_for_gpio_bits[16]	auto[1]	auto[1]	5769632	1			T19	351		T20	1598		T21	47681
bins_for_gpio_bits[17]	auto[0]	auto[0]	8976194	1			T19	96		T20	445		T21	103255
bins_for_gpio_bits[17]	auto[0]	auto[1]	270724	1			T19	11		T20	63		T21	3603
bins_for_gpio_bits[17]	auto[1]	auto[0]	271054	1			T19	11		T20	62		T21	3604
bins_for_gpio_bits[17]	auto[1]	auto[1]	5765259	1			T19	354		T20	1586		T21	47441
bins_for_gpio_bits[18]	auto[0]	auto[0]	8971524	1			T19	104		T20	363		T21	102629
bins_for_gpio_bits[18]	auto[0]	auto[1]	270120	1			T19	12		T20	51		T21	3669
bins_for_gpio_bits[18]	auto[1]	auto[0]	270380	1			T19	12		T20	50		T21	3669
bins_for_gpio_bits[18]	auto[1]	auto[1]	5771207	1			T19	344		T20	1692		T21	47936
bins_for_gpio_bits[19]	auto[0]	auto[0]	8972858	1			T19	87		T20	295		T21	103342
bins_for_gpio_bits[19]	auto[0]	auto[1]	270768	1			T19	10		T20	40		T21	3610
bins_for_gpio_bits[19]	auto[1]	auto[0]	271066	1			T19	10		T20	40		T21	3610
bins_for_gpio_bits[19]	auto[1]	auto[1]	5768539	1			T19	365		T20	1781		T21	47341
bins_for_gpio_bits[20]	auto[0]	auto[0]	8968772	1			T19	127		T20	448		T21	102957
bins_for_gpio_bits[20]	auto[0]	auto[1]	271300	1			T19	10		T20	71		T21	3571
bins_for_gpio_bits[20]	auto[1]	auto[0]	271599	1			T19	10		T20	70		T21	3571
bins_for_gpio_bits[20]	auto[1]	auto[1]	5771560	1			T19	325		T20	1567		T21	47804
bins_for_gpio_bits[21]	auto[0]	auto[0]	8986829	1			T19	82		T20	416		T21	103641
bins_for_gpio_bits[21]	auto[0]	auto[1]	270944	1			T19	8		T20	58		T21	3600
bins_for_gpio_bits[21]	auto[1]	auto[0]	271253	1			T19	8		T20	58		T21	3601
bins_for_gpio_bits[21]	auto[1]	auto[1]	5754205	1			T19	374		T20	1624		T21	47061
bins_for_gpio_bits[22]	auto[0]	auto[0]	8972414	1			T19	79		T20	429		T21	102396
bins_for_gpio_bits[22]	auto[0]	auto[1]	271438	1			T19	6		T20	58		T21	3690
bins_for_gpio_bits[22]	auto[1]	auto[0]	271697	1			T19	6		T20	58		T21	3691
bins_for_gpio_bits[22]	auto[1]	auto[1]	5767682	1			T19	381		T20	1611		T21	48126
bins_for_gpio_bits[23]	auto[0]	auto[0]	8974472	1			T19	87		T20	399		T21	102972
bins_for_gpio_bits[23]	auto[0]	auto[1]	271225	1			T19	5		T20	62		T21	3630
bins_for_gpio_bits[23]	auto[1]	auto[0]	271540	1			T19	4		T20	62		T21	3631
bins_for_gpio_bits[23]	auto[1]	auto[1]	5765994	1			T19	376		T20	1633		T21	47670
bins_for_gpio_bits[24]	auto[0]	auto[0]	8978318	1			T19	115		T20	468		T21	102379
bins_for_gpio_bits[24]	auto[0]	auto[1]	271303	1			T19	12		T20	65		T21	3646
bins_for_gpio_bits[24]	auto[1]	auto[0]	271589	1			T19	12		T20	65		T21	3647
bins_for_gpio_bits[24]	auto[1]	auto[1]	5762021	1			T19	333		T20	1558		T21	48231
bins_for_gpio_bits[25]	auto[0]	auto[0]	8977464	1			T19	99		T20	346		T21	102165
bins_for_gpio_bits[25]	auto[0]	auto[1]	270468	1			T19	10		T20	50		T21	3651
bins_for_gpio_bits[25]	auto[1]	auto[0]	270740	1			T19	10		T20	50		T21	3651
bins_for_gpio_bits[25]	auto[1]	auto[1]	5764559	1			T19	353		T20	1710		T21	48436
bins_for_gpio_bits[26]	auto[0]	auto[0]	8966672	1			T19	123		T20	443		T21	102873
bins_for_gpio_bits[26]	auto[0]	auto[1]	271766	1			T19	10		T20	60		T21	3610
bins_for_gpio_bits[26]	auto[1]	auto[0]	272035	1			T19	10		T20	60		T21	3611
bins_for_gpio_bits[26]	auto[1]	auto[1]	5772758	1			T19	329		T20	1593		T21	47809
bins_for_gpio_bits[27]	auto[0]	auto[0]	8988733	1			T19	120		T20	421		T21	102576
bins_for_gpio_bits[27]	auto[0]	auto[1]	271165	1			T19	10		T20	66		T21	3710
bins_for_gpio_bits[27]	auto[1]	auto[0]	271443	1			T19	10		T20	66		T21	3710
bins_for_gpio_bits[27]	auto[1]	auto[1]	5751890	1			T19	332		T20	1603		T21	47907
bins_for_gpio_bits[28]	auto[0]	auto[0]	8970679	1			T19	126		T20	479		T21	103110
bins_for_gpio_bits[28]	auto[0]	auto[1]	271190	1			T19	11		T20	70		T21	3629
bins_for_gpio_bits[28]	auto[1]	auto[0]	271475	1			T19	10		T20	70		T21	3629
bins_for_gpio_bits[28]	auto[1]	auto[1]	5769887	1			T19	325		T20	1537		T21	47535
bins_for_gpio_bits[29]	auto[0]	auto[0]	8977274	1			T19	102		T20	550		T21	102646
bins_for_gpio_bits[29]	auto[0]	auto[1]	270467	1			T19	8		T20	64		T21	3644
bins_for_gpio_bits[29]	auto[1]	auto[0]	270766	1			T19	8		T20	64		T21	3645
bins_for_gpio_bits[29]	auto[1]	auto[1]	5764724	1			T19	354		T20	1478		T21	47968
bins_for_gpio_bits[30]	auto[0]	auto[0]	8969960	1			T19	114		T20	535		T21	103204
bins_for_gpio_bits[30]	auto[0]	auto[1]	270622	1			T19	9		T20	70		T21	3630
bins_for_gpio_bits[30]	auto[1]	auto[0]	270913	1			T19	9		T20	69		T21	3630
bins_for_gpio_bits[30]	auto[1]	auto[1]	5771736	1			T19	340		T20	1482		T21	47439
bins_for_gpio_bits[31]	auto[0]	auto[0]	8963824	1			T19	105		T20	387		T21	102877
bins_for_gpio_bits[31]	auto[0]	auto[1]	271394	1			T19	13		T20	63		T21	3688
bins_for_gpio_bits[31]	auto[1]	auto[0]	271679	1			T19	13		T20	63		T21	3689
bins_for_gpio_bits[31]	auto[1]	auto[1]	5776334	1			T19	341		T20	1643		T21	47649