Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8922129 |
1 |
|
|
T19 |
240 |
|
T20 |
1299 |
|
T21 |
80603 |
| auto[1] |
6573404 |
1 |
|
|
T20 |
992 |
|
T21 |
78641 |
|
T1 |
40381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14644370 |
1 |
|
|
T19 |
240 |
|
T20 |
2243 |
|
T21 |
149772 |
| auto[1] |
851163 |
1 |
|
|
T20 |
48 |
|
T21 |
9472 |
|
T1 |
5663 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8902268 |
1 |
|
|
T19 |
240 |
|
T20 |
1103 |
|
T21 |
78480 |
| auto[1] |
6593265 |
1 |
|
|
T20 |
1188 |
|
T21 |
80764 |
|
T1 |
42465 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2871364 |
1 |
|
|
T20 |
626 |
|
T21 |
35082 |
|
T1 |
18899 |
| auto[1] |
auto[0] |
auto[1] |
425129 |
1 |
|
|
T20 |
22 |
|
T21 |
4732 |
|
T1 |
2933 |
| auto[1] |
auto[1] |
auto[0] |
2870738 |
1 |
|
|
T20 |
514 |
|
T21 |
36210 |
|
T1 |
17903 |
| auto[1] |
auto[1] |
auto[1] |
426034 |
1 |
|
|
T20 |
26 |
|
T21 |
4740 |
|
T1 |
2730 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8907855 |
1 |
|
|
T19 |
240 |
|
T20 |
1242 |
|
T21 |
79244 |
| auto[1] |
6587678 |
1 |
|
|
T20 |
1049 |
|
T21 |
80000 |
|
T1 |
40108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14648153 |
1 |
|
|
T19 |
240 |
|
T20 |
2242 |
|
T21 |
150267 |
| auto[1] |
847380 |
1 |
|
|
T20 |
49 |
|
T21 |
8977 |
|
T1 |
4873 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919988 |
1 |
|
|
T19 |
240 |
|
T20 |
1086 |
|
T21 |
80412 |
| auto[1] |
6575545 |
1 |
|
|
T20 |
1205 |
|
T21 |
78832 |
|
T1 |
38038 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2877144 |
1 |
|
|
T20 |
625 |
|
T21 |
35003 |
|
T1 |
16631 |
| auto[1] |
auto[0] |
auto[1] |
425980 |
1 |
|
|
T20 |
28 |
|
T21 |
4439 |
|
T1 |
2501 |
| auto[1] |
auto[1] |
auto[0] |
2851021 |
1 |
|
|
T20 |
531 |
|
T21 |
34852 |
|
T1 |
16534 |
| auto[1] |
auto[1] |
auto[1] |
421400 |
1 |
|
|
T20 |
21 |
|
T21 |
4538 |
|
T1 |
2372 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8903390 |
1 |
|
|
T19 |
240 |
|
T20 |
1256 |
|
T21 |
76027 |
| auto[1] |
6592143 |
1 |
|
|
T20 |
1035 |
|
T21 |
83217 |
|
T1 |
41411 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14647076 |
1 |
|
|
T19 |
240 |
|
T20 |
2252 |
|
T21 |
149804 |
| auto[1] |
848457 |
1 |
|
|
T20 |
39 |
|
T21 |
9440 |
|
T1 |
5182 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8911733 |
1 |
|
|
T19 |
240 |
|
T20 |
1316 |
|
T21 |
77755 |
| auto[1] |
6583800 |
1 |
|
|
T20 |
975 |
|
T21 |
81489 |
|
T1 |
40132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2854538 |
1 |
|
|
T20 |
497 |
|
T21 |
33393 |
|
T1 |
17170 |
| auto[1] |
auto[0] |
auto[1] |
422020 |
1 |
|
|
T20 |
25 |
|
T21 |
4228 |
|
T1 |
2630 |
| auto[1] |
auto[1] |
auto[0] |
2880805 |
1 |
|
|
T20 |
439 |
|
T21 |
38656 |
|
T1 |
17780 |
| auto[1] |
auto[1] |
auto[1] |
426437 |
1 |
|
|
T20 |
14 |
|
T21 |
5212 |
|
T1 |
2552 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8892077 |
1 |
|
|
T19 |
240 |
|
T20 |
1172 |
|
T21 |
82929 |
| auto[1] |
6603456 |
1 |
|
|
T20 |
1119 |
|
T21 |
76315 |
|
T1 |
41241 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14643382 |
1 |
|
|
T19 |
240 |
|
T20 |
2252 |
|
T21 |
149708 |
| auto[1] |
852151 |
1 |
|
|
T20 |
39 |
|
T21 |
9536 |
|
T1 |
4597 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8886667 |
1 |
|
|
T19 |
240 |
|
T20 |
1073 |
|
T21 |
78385 |
| auto[1] |
6608866 |
1 |
|
|
T20 |
1218 |
|
T21 |
80859 |
|
T1 |
37223 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2867731 |
1 |
|
|
T20 |
566 |
|
T21 |
36051 |
|
T1 |
16139 |
| auto[1] |
auto[0] |
auto[1] |
424397 |
1 |
|
|
T20 |
20 |
|
T21 |
5011 |
|
T1 |
2241 |
| auto[1] |
auto[1] |
auto[0] |
2888984 |
1 |
|
|
T20 |
613 |
|
T21 |
35272 |
|
T1 |
16487 |
| auto[1] |
auto[1] |
auto[1] |
427754 |
1 |
|
|
T20 |
19 |
|
T21 |
4525 |
|
T1 |
2356 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933615 |
1 |
|
|
T19 |
240 |
|
T20 |
1186 |
|
T21 |
81193 |
| auto[1] |
6561918 |
1 |
|
|
T20 |
1105 |
|
T21 |
78051 |
|
T1 |
44411 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14644761 |
1 |
|
|
T19 |
240 |
|
T20 |
2250 |
|
T21 |
150292 |
| auto[1] |
850772 |
1 |
|
|
T20 |
41 |
|
T21 |
8952 |
|
T1 |
4604 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910267 |
1 |
|
|
T19 |
240 |
|
T20 |
1281 |
|
T21 |
81743 |
| auto[1] |
6585266 |
1 |
|
|
T20 |
1010 |
|
T21 |
77501 |
|
T1 |
36212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2893240 |
1 |
|
|
T20 |
542 |
|
T21 |
36384 |
|
T1 |
15069 |
| auto[1] |
auto[0] |
auto[1] |
430162 |
1 |
|
|
T20 |
24 |
|
T21 |
4799 |
|
T1 |
2112 |
| auto[1] |
auto[1] |
auto[0] |
2841254 |
1 |
|
|
T20 |
427 |
|
T21 |
32165 |
|
T1 |
16539 |
| auto[1] |
auto[1] |
auto[1] |
420610 |
1 |
|
|
T20 |
17 |
|
T21 |
4153 |
|
T1 |
2492 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8906487 |
1 |
|
|
T19 |
240 |
|
T20 |
1178 |
|
T21 |
81100 |
| auto[1] |
6589046 |
1 |
|
|
T20 |
1113 |
|
T21 |
78144 |
|
T1 |
42532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14649935 |
1 |
|
|
T19 |
240 |
|
T20 |
2257 |
|
T21 |
150701 |
| auto[1] |
845598 |
1 |
|
|
T20 |
34 |
|
T21 |
8543 |
|
T1 |
5693 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931084 |
1 |
|
|
T19 |
240 |
|
T20 |
1129 |
|
T21 |
83125 |
| auto[1] |
6564449 |
1 |
|
|
T20 |
1162 |
|
T21 |
76119 |
|
T1 |
42412 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2863491 |
1 |
|
|
T20 |
567 |
|
T21 |
34521 |
|
T1 |
16339 |
| auto[1] |
auto[0] |
auto[1] |
424061 |
1 |
|
|
T20 |
20 |
|
T21 |
4355 |
|
T1 |
2487 |
| auto[1] |
auto[1] |
auto[0] |
2855360 |
1 |
|
|
T20 |
561 |
|
T21 |
33055 |
|
T1 |
20380 |
| auto[1] |
auto[1] |
auto[1] |
421537 |
1 |
|
|
T20 |
14 |
|
T21 |
4188 |
|
T1 |
3206 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8903980 |
1 |
|
|
T19 |
240 |
|
T20 |
1263 |
|
T21 |
79061 |
| auto[1] |
6591553 |
1 |
|
|
T20 |
1028 |
|
T21 |
80183 |
|
T1 |
41375 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14648310 |
1 |
|
|
T19 |
240 |
|
T20 |
2242 |
|
T21 |
150524 |
| auto[1] |
847223 |
1 |
|
|
T20 |
49 |
|
T21 |
8720 |
|
T1 |
4541 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8926369 |
1 |
|
|
T19 |
240 |
|
T20 |
1011 |
|
T21 |
81683 |
| auto[1] |
6569164 |
1 |
|
|
T20 |
1280 |
|
T21 |
77561 |
|
T1 |
35768 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2854861 |
1 |
|
|
T20 |
678 |
|
T21 |
33255 |
|
T1 |
15037 |
| auto[1] |
auto[0] |
auto[1] |
422122 |
1 |
|
|
T20 |
30 |
|
T21 |
4237 |
|
T1 |
2191 |
| auto[1] |
auto[1] |
auto[0] |
2867080 |
1 |
|
|
T20 |
553 |
|
T21 |
35586 |
|
T1 |
16190 |
| auto[1] |
auto[1] |
auto[1] |
425101 |
1 |
|
|
T20 |
19 |
|
T21 |
4483 |
|
T1 |
2350 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8895149 |
1 |
|
|
T19 |
240 |
|
T20 |
1226 |
|
T21 |
81369 |
| auto[1] |
6600384 |
1 |
|
|
T20 |
1065 |
|
T21 |
77875 |
|
T1 |
46159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14650639 |
1 |
|
|
T19 |
240 |
|
T20 |
2244 |
|
T21 |
149585 |
| auto[1] |
844894 |
1 |
|
|
T20 |
47 |
|
T21 |
9659 |
|
T1 |
5360 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8932269 |
1 |
|
|
T19 |
240 |
|
T20 |
1331 |
|
T21 |
76136 |
| auto[1] |
6563264 |
1 |
|
|
T20 |
960 |
|
T21 |
83108 |
|
T1 |
40010 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2855459 |
1 |
|
|
T20 |
479 |
|
T21 |
38741 |
|
T1 |
15242 |
| auto[1] |
auto[0] |
auto[1] |
421310 |
1 |
|
|
T20 |
23 |
|
T21 |
5216 |
|
T1 |
2320 |
| auto[1] |
auto[1] |
auto[0] |
2862911 |
1 |
|
|
T20 |
434 |
|
T21 |
34708 |
|
T1 |
19408 |
| auto[1] |
auto[1] |
auto[1] |
423584 |
1 |
|
|
T20 |
24 |
|
T21 |
4443 |
|
T1 |
3040 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8959842 |
1 |
|
|
T19 |
240 |
|
T20 |
1158 |
|
T21 |
82761 |
| auto[1] |
6535691 |
1 |
|
|
T20 |
1133 |
|
T21 |
76483 |
|
T1 |
41090 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14649257 |
1 |
|
|
T19 |
240 |
|
T20 |
2241 |
|
T21 |
149891 |
| auto[1] |
846276 |
1 |
|
|
T20 |
50 |
|
T21 |
9353 |
|
T1 |
5140 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928371 |
1 |
|
|
T19 |
240 |
|
T20 |
964 |
|
T21 |
78304 |
| auto[1] |
6567162 |
1 |
|
|
T20 |
1327 |
|
T21 |
80940 |
|
T1 |
39267 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2883870 |
1 |
|
|
T20 |
662 |
|
T21 |
36352 |
|
T1 |
16206 |
| auto[1] |
auto[0] |
auto[1] |
426725 |
1 |
|
|
T20 |
25 |
|
T21 |
4679 |
|
T1 |
2401 |
| auto[1] |
auto[1] |
auto[0] |
2837016 |
1 |
|
|
T20 |
615 |
|
T21 |
35235 |
|
T1 |
17921 |
| auto[1] |
auto[1] |
auto[1] |
419551 |
1 |
|
|
T20 |
25 |
|
T21 |
4674 |
|
T1 |
2739 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8926203 |
1 |
|
|
T19 |
240 |
|
T20 |
1019 |
|
T21 |
80978 |
| auto[1] |
6569330 |
1 |
|
|
T20 |
1272 |
|
T21 |
78266 |
|
T1 |
38930 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14648091 |
1 |
|
|
T19 |
240 |
|
T20 |
2251 |
|
T21 |
150112 |
| auto[1] |
847442 |
1 |
|
|
T20 |
40 |
|
T21 |
9132 |
|
T1 |
4785 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8917484 |
1 |
|
|
T19 |
240 |
|
T20 |
1132 |
|
T21 |
79941 |
| auto[1] |
6578049 |
1 |
|
|
T20 |
1159 |
|
T21 |
79303 |
|
T1 |
37173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2867124 |
1 |
|
|
T20 |
467 |
|
T21 |
34029 |
|
T1 |
17124 |
| auto[1] |
auto[0] |
auto[1] |
423253 |
1 |
|
|
T20 |
17 |
|
T21 |
4462 |
|
T1 |
2655 |
| auto[1] |
auto[1] |
auto[0] |
2863483 |
1 |
|
|
T20 |
652 |
|
T21 |
36142 |
|
T1 |
15264 |
| auto[1] |
auto[1] |
auto[1] |
424189 |
1 |
|
|
T20 |
23 |
|
T21 |
4670 |
|
T1 |
2130 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8867885 |
1 |
|
|
T19 |
240 |
|
T20 |
1241 |
|
T21 |
78110 |
| auto[1] |
6627648 |
1 |
|
|
T20 |
1050 |
|
T21 |
81134 |
|
T1 |
45457 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14652037 |
1 |
|
|
T19 |
240 |
|
T20 |
2253 |
|
T21 |
150380 |
| auto[1] |
843496 |
1 |
|
|
T20 |
38 |
|
T21 |
8864 |
|
T1 |
5138 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940282 |
1 |
|
|
T19 |
240 |
|
T20 |
1251 |
|
T21 |
81814 |
| auto[1] |
6555251 |
1 |
|
|
T20 |
1040 |
|
T21 |
77430 |
|
T1 |
39590 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2846907 |
1 |
|
|
T20 |
530 |
|
T21 |
35473 |
|
T1 |
16117 |
| auto[1] |
auto[0] |
auto[1] |
420123 |
1 |
|
|
T20 |
22 |
|
T21 |
4675 |
|
T1 |
2383 |
| auto[1] |
auto[1] |
auto[0] |
2864848 |
1 |
|
|
T20 |
472 |
|
T21 |
33093 |
|
T1 |
18335 |
| auto[1] |
auto[1] |
auto[1] |
423373 |
1 |
|
|
T20 |
16 |
|
T21 |
4189 |
|
T1 |
2755 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8912750 |
1 |
|
|
T19 |
240 |
|
T20 |
1152 |
|
T21 |
80392 |
| auto[1] |
6582783 |
1 |
|
|
T20 |
1139 |
|
T21 |
78852 |
|
T1 |
39728 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14645623 |
1 |
|
|
T19 |
240 |
|
T20 |
2260 |
|
T21 |
150697 |
| auto[1] |
849910 |
1 |
|
|
T20 |
31 |
|
T21 |
8547 |
|
T1 |
5352 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8904070 |
1 |
|
|
T19 |
240 |
|
T20 |
1039 |
|
T21 |
82584 |
| auto[1] |
6591463 |
1 |
|
|
T20 |
1252 |
|
T21 |
76660 |
|
T1 |
40930 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2885110 |
1 |
|
|
T20 |
638 |
|
T21 |
33328 |
|
T1 |
18762 |
| auto[1] |
auto[0] |
auto[1] |
426513 |
1 |
|
|
T20 |
19 |
|
T21 |
4072 |
|
T1 |
2948 |
| auto[1] |
auto[1] |
auto[0] |
2856443 |
1 |
|
|
T20 |
583 |
|
T21 |
34785 |
|
T1 |
16816 |
| auto[1] |
auto[1] |
auto[1] |
423397 |
1 |
|
|
T20 |
12 |
|
T21 |
4475 |
|
T1 |
2404 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8896822 |
1 |
|
|
T19 |
240 |
|
T20 |
1214 |
|
T21 |
80086 |
| auto[1] |
6598711 |
1 |
|
|
T20 |
1077 |
|
T21 |
79158 |
|
T1 |
39097 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14647482 |
1 |
|
|
T19 |
240 |
|
T20 |
2252 |
|
T21 |
149943 |
| auto[1] |
848051 |
1 |
|
|
T20 |
39 |
|
T21 |
9301 |
|
T1 |
4616 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8911323 |
1 |
|
|
T19 |
240 |
|
T20 |
1225 |
|
T21 |
79546 |
| auto[1] |
6584210 |
1 |
|
|
T20 |
1066 |
|
T21 |
79698 |
|
T1 |
36686 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2854362 |
1 |
|
|
T20 |
535 |
|
T21 |
34337 |
|
T1 |
15576 |
| auto[1] |
auto[0] |
auto[1] |
420682 |
1 |
|
|
T20 |
22 |
|
T21 |
4485 |
|
T1 |
2269 |
| auto[1] |
auto[1] |
auto[0] |
2881797 |
1 |
|
|
T20 |
492 |
|
T21 |
36060 |
|
T1 |
16494 |
| auto[1] |
auto[1] |
auto[1] |
427369 |
1 |
|
|
T20 |
17 |
|
T21 |
4816 |
|
T1 |
2347 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8934946 |
1 |
|
|
T19 |
240 |
|
T20 |
1036 |
|
T21 |
82932 |
| auto[1] |
6560587 |
1 |
|
|
T20 |
1255 |
|
T21 |
76312 |
|
T1 |
41986 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14653550 |
1 |
|
|
T19 |
240 |
|
T20 |
2231 |
|
T21 |
150136 |
| auto[1] |
841983 |
1 |
|
|
T20 |
60 |
|
T21 |
9108 |
|
T1 |
5493 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8953130 |
1 |
|
|
T19 |
240 |
|
T20 |
1039 |
|
T21 |
80221 |
| auto[1] |
6542403 |
1 |
|
|
T20 |
1252 |
|
T21 |
79023 |
|
T1 |
42162 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2872575 |
1 |
|
|
T20 |
549 |
|
T21 |
35719 |
|
T1 |
18019 |
| auto[1] |
auto[0] |
auto[1] |
425234 |
1 |
|
|
T20 |
27 |
|
T21 |
4646 |
|
T1 |
2688 |
| auto[1] |
auto[1] |
auto[0] |
2827845 |
1 |
|
|
T20 |
643 |
|
T21 |
34196 |
|
T1 |
18650 |
| auto[1] |
auto[1] |
auto[1] |
416749 |
1 |
|
|
T20 |
33 |
|
T21 |
4462 |
|
T1 |
2805 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930304 |
1 |
|
|
T19 |
240 |
|
T20 |
1106 |
|
T21 |
79132 |
| auto[1] |
6565229 |
1 |
|
|
T20 |
1185 |
|
T21 |
80112 |
|
T1 |
42509 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14645656 |
1 |
|
|
T19 |
240 |
|
T20 |
2250 |
|
T21 |
150279 |
| auto[1] |
849877 |
1 |
|
|
T20 |
41 |
|
T21 |
8965 |
|
T1 |
5569 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8908800 |
1 |
|
|
T19 |
240 |
|
T20 |
1182 |
|
T21 |
80564 |
| auto[1] |
6586733 |
1 |
|
|
T20 |
1109 |
|
T21 |
78680 |
|
T1 |
43178 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2880083 |
1 |
|
|
T20 |
512 |
|
T21 |
33638 |
|
T1 |
17849 |
| auto[1] |
auto[0] |
auto[1] |
426998 |
1 |
|
|
T20 |
17 |
|
T21 |
4151 |
|
T1 |
2501 |
| auto[1] |
auto[1] |
auto[0] |
2856773 |
1 |
|
|
T20 |
556 |
|
T21 |
36077 |
|
T1 |
19760 |
| auto[1] |
auto[1] |
auto[1] |
422879 |
1 |
|
|
T20 |
24 |
|
T21 |
4814 |
|
T1 |
3068 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919121 |
1 |
|
|
T19 |
240 |
|
T20 |
1127 |
|
T21 |
83284 |
| auto[1] |
6576412 |
1 |
|
|
T20 |
1164 |
|
T21 |
75960 |
|
T1 |
39977 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14651375 |
1 |
|
|
T19 |
240 |
|
T20 |
2242 |
|
T21 |
149782 |
| auto[1] |
844158 |
1 |
|
|
T20 |
49 |
|
T21 |
9462 |
|
T1 |
5628 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940066 |
1 |
|
|
T19 |
240 |
|
T20 |
1033 |
|
T21 |
77959 |
| auto[1] |
6555467 |
1 |
|
|
T20 |
1258 |
|
T21 |
81285 |
|
T1 |
42942 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2845559 |
1 |
|
|
T20 |
546 |
|
T21 |
35803 |
|
T1 |
18306 |
| auto[1] |
auto[0] |
auto[1] |
420391 |
1 |
|
|
T20 |
18 |
|
T21 |
4734 |
|
T1 |
2698 |
| auto[1] |
auto[1] |
auto[0] |
2865750 |
1 |
|
|
T20 |
663 |
|
T21 |
36020 |
|
T1 |
19008 |
| auto[1] |
auto[1] |
auto[1] |
423767 |
1 |
|
|
T20 |
31 |
|
T21 |
4728 |
|
T1 |
2930 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910316 |
1 |
|
|
T19 |
240 |
|
T20 |
1136 |
|
T21 |
83617 |
| auto[1] |
6585217 |
1 |
|
|
T20 |
1155 |
|
T21 |
75627 |
|
T1 |
36487 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14645402 |
1 |
|
|
T19 |
240 |
|
T20 |
2241 |
|
T21 |
150035 |
| auto[1] |
850131 |
1 |
|
|
T20 |
50 |
|
T21 |
9209 |
|
T1 |
5160 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8911470 |
1 |
|
|
T19 |
240 |
|
T20 |
1090 |
|
T21 |
79648 |
| auto[1] |
6584063 |
1 |
|
|
T20 |
1201 |
|
T21 |
79596 |
|
T1 |
39805 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2869553 |
1 |
|
|
T20 |
571 |
|
T21 |
37384 |
|
T1 |
18896 |
| auto[1] |
auto[0] |
auto[1] |
425283 |
1 |
|
|
T20 |
24 |
|
T21 |
5114 |
|
T1 |
2846 |
| auto[1] |
auto[1] |
auto[0] |
2864379 |
1 |
|
|
T20 |
580 |
|
T21 |
33003 |
|
T1 |
15749 |
| auto[1] |
auto[1] |
auto[1] |
424848 |
1 |
|
|
T20 |
26 |
|
T21 |
4095 |
|
T1 |
2314 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8934298 |
1 |
|
|
T19 |
240 |
|
T20 |
1112 |
|
T21 |
83105 |
| auto[1] |
6561235 |
1 |
|
|
T20 |
1179 |
|
T21 |
76139 |
|
T1 |
40173 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14641887 |
1 |
|
|
T19 |
240 |
|
T20 |
2247 |
|
T21 |
149981 |
| auto[1] |
853646 |
1 |
|
|
T20 |
44 |
|
T21 |
9263 |
|
T1 |
4700 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8893455 |
1 |
|
|
T19 |
240 |
|
T20 |
1161 |
|
T21 |
80734 |
| auto[1] |
6602078 |
1 |
|
|
T20 |
1130 |
|
T21 |
78510 |
|
T1 |
36319 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2884202 |
1 |
|
|
T20 |
506 |
|
T21 |
34642 |
|
T1 |
15375 |
| auto[1] |
auto[0] |
auto[1] |
427895 |
1 |
|
|
T20 |
21 |
|
T21 |
4783 |
|
T1 |
2215 |
| auto[1] |
auto[1] |
auto[0] |
2864230 |
1 |
|
|
T20 |
580 |
|
T21 |
34605 |
|
T1 |
16244 |
| auto[1] |
auto[1] |
auto[1] |
425751 |
1 |
|
|
T20 |
23 |
|
T21 |
4480 |
|
T1 |
2485 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928070 |
1 |
|
|
T19 |
240 |
|
T20 |
1123 |
|
T21 |
80129 |
| auto[1] |
6567463 |
1 |
|
|
T20 |
1168 |
|
T21 |
79115 |
|
T1 |
39784 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14644833 |
1 |
|
|
T19 |
240 |
|
T20 |
2251 |
|
T21 |
149931 |
| auto[1] |
850700 |
1 |
|
|
T20 |
40 |
|
T21 |
9313 |
|
T1 |
5199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8901063 |
1 |
|
|
T19 |
240 |
|
T20 |
1098 |
|
T21 |
78688 |
| auto[1] |
6594470 |
1 |
|
|
T20 |
1193 |
|
T21 |
80556 |
|
T1 |
39948 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2877958 |
1 |
|
|
T20 |
554 |
|
T21 |
35829 |
|
T1 |
16625 |
| auto[1] |
auto[0] |
auto[1] |
426189 |
1 |
|
|
T20 |
17 |
|
T21 |
4828 |
|
T1 |
2450 |
| auto[1] |
auto[1] |
auto[0] |
2865812 |
1 |
|
|
T20 |
599 |
|
T21 |
35414 |
|
T1 |
18124 |
| auto[1] |
auto[1] |
auto[1] |
424511 |
1 |
|
|
T20 |
23 |
|
T21 |
4485 |
|
T1 |
2749 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |