Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8922129 |
1 |
|
|
T19 |
240 |
|
T20 |
1299 |
|
T21 |
80603 |
auto[1] |
6573404 |
1 |
|
|
T20 |
992 |
|
T21 |
78641 |
|
T1 |
40381 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12809395 |
1 |
|
|
T19 |
240 |
|
T20 |
1471 |
|
T21 |
130035 |
auto[1] |
2686138 |
1 |
|
|
T20 |
820 |
|
T21 |
29209 |
|
T1 |
14848 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8919769 |
1 |
|
|
T19 |
240 |
|
T20 |
1156 |
|
T21 |
78360 |
auto[1] |
6575764 |
1 |
|
|
T20 |
1135 |
|
T21 |
80884 |
|
T1 |
39366 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1950212 |
1 |
|
|
T20 |
201 |
|
T21 |
27951 |
|
T1 |
13465 |
auto[1] |
auto[0] |
auto[1] |
1347254 |
1 |
|
|
T20 |
412 |
|
T21 |
15639 |
|
T1 |
8043 |
auto[1] |
auto[1] |
auto[0] |
1939414 |
1 |
|
|
T20 |
114 |
|
T21 |
23724 |
|
T1 |
11053 |
auto[1] |
auto[1] |
auto[1] |
1338884 |
1 |
|
|
T20 |
408 |
|
T21 |
13570 |
|
T1 |
6805 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |