Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8892077 |
1 |
|
|
T19 |
240 |
|
T20 |
1172 |
|
T21 |
82929 |
auto[1] |
6603456 |
1 |
|
|
T20 |
1119 |
|
T21 |
76315 |
|
T1 |
41241 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12814575 |
1 |
|
|
T19 |
240 |
|
T20 |
1443 |
|
T21 |
130171 |
auto[1] |
2680958 |
1 |
|
|
T20 |
848 |
|
T21 |
29073 |
|
T1 |
14589 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8926417 |
1 |
|
|
T19 |
240 |
|
T20 |
1205 |
|
T21 |
78807 |
auto[1] |
6569116 |
1 |
|
|
T20 |
1086 |
|
T21 |
80437 |
|
T1 |
39697 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1948499 |
1 |
|
|
T20 |
101 |
|
T21 |
27539 |
|
T1 |
13091 |
auto[1] |
auto[0] |
auto[1] |
1340237 |
1 |
|
|
T20 |
430 |
|
T21 |
15670 |
|
T1 |
7378 |
auto[1] |
auto[1] |
auto[0] |
1939659 |
1 |
|
|
T20 |
137 |
|
T21 |
23825 |
|
T1 |
12017 |
auto[1] |
auto[1] |
auto[1] |
1340721 |
1 |
|
|
T20 |
418 |
|
T21 |
13403 |
|
T1 |
7211 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |