Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8933615 |
1 |
|
|
T19 |
240 |
|
T20 |
1186 |
|
T21 |
81193 |
auto[1] |
6561918 |
1 |
|
|
T20 |
1105 |
|
T21 |
78051 |
|
T1 |
44411 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12823113 |
1 |
|
|
T19 |
240 |
|
T20 |
1470 |
|
T21 |
131823 |
auto[1] |
2672420 |
1 |
|
|
T20 |
821 |
|
T21 |
27421 |
|
T1 |
15307 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8942290 |
1 |
|
|
T19 |
240 |
|
T20 |
1220 |
|
T21 |
82183 |
auto[1] |
6553243 |
1 |
|
|
T20 |
1071 |
|
T21 |
77061 |
|
T1 |
41197 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1950305 |
1 |
|
|
T20 |
111 |
|
T21 |
25248 |
|
T1 |
11901 |
auto[1] |
auto[0] |
auto[1] |
1345105 |
1 |
|
|
T20 |
459 |
|
T21 |
13906 |
|
T1 |
7038 |
auto[1] |
auto[1] |
auto[0] |
1930518 |
1 |
|
|
T20 |
139 |
|
T21 |
24392 |
|
T1 |
13989 |
auto[1] |
auto[1] |
auto[1] |
1327315 |
1 |
|
|
T20 |
362 |
|
T21 |
13515 |
|
T1 |
8269 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |