Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8903980 |
1 |
|
|
T19 |
240 |
|
T20 |
1263 |
|
T21 |
79061 |
auto[1] |
6591553 |
1 |
|
|
T20 |
1028 |
|
T21 |
80183 |
|
T1 |
41375 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12821149 |
1 |
|
|
T19 |
240 |
|
T20 |
1387 |
|
T21 |
130779 |
auto[1] |
2674384 |
1 |
|
|
T20 |
904 |
|
T21 |
28465 |
|
T1 |
15840 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8924620 |
1 |
|
|
T19 |
240 |
|
T20 |
1098 |
|
T21 |
78803 |
auto[1] |
6570913 |
1 |
|
|
T20 |
1193 |
|
T21 |
80441 |
|
T1 |
43067 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1943447 |
1 |
|
|
T20 |
149 |
|
T21 |
25518 |
|
T1 |
14349 |
auto[1] |
auto[0] |
auto[1] |
1332735 |
1 |
|
|
T20 |
452 |
|
T21 |
13980 |
|
T1 |
8233 |
auto[1] |
auto[1] |
auto[0] |
1953082 |
1 |
|
|
T20 |
140 |
|
T21 |
26458 |
|
T1 |
12878 |
auto[1] |
auto[1] |
auto[1] |
1341649 |
1 |
|
|
T20 |
452 |
|
T21 |
14485 |
|
T1 |
7607 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |