Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8895149 |
1 |
|
|
T19 |
240 |
|
T20 |
1226 |
|
T21 |
81369 |
auto[1] |
6600384 |
1 |
|
|
T20 |
1065 |
|
T21 |
77875 |
|
T1 |
46159 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12821009 |
1 |
|
|
T19 |
240 |
|
T20 |
1344 |
|
T21 |
131718 |
auto[1] |
2674524 |
1 |
|
|
T20 |
947 |
|
T21 |
27526 |
|
T1 |
15473 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8921348 |
1 |
|
|
T19 |
240 |
|
T20 |
1024 |
|
T21 |
83539 |
auto[1] |
6574185 |
1 |
|
|
T20 |
1267 |
|
T21 |
75705 |
|
T1 |
42954 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1940902 |
1 |
|
|
T20 |
146 |
|
T21 |
24117 |
|
T1 |
11456 |
auto[1] |
auto[0] |
auto[1] |
1336382 |
1 |
|
|
T20 |
471 |
|
T21 |
13438 |
|
T1 |
6714 |
auto[1] |
auto[1] |
auto[0] |
1958759 |
1 |
|
|
T20 |
174 |
|
T21 |
24062 |
|
T1 |
16025 |
auto[1] |
auto[1] |
auto[1] |
1338142 |
1 |
|
|
T20 |
476 |
|
T21 |
14088 |
|
T1 |
8759 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |