Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8959842 |
1 |
|
|
T19 |
240 |
|
T20 |
1158 |
|
T21 |
82761 |
auto[1] |
6535691 |
1 |
|
|
T20 |
1133 |
|
T21 |
76483 |
|
T1 |
41090 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12812116 |
1 |
|
|
T19 |
240 |
|
T20 |
1483 |
|
T21 |
131058 |
auto[1] |
2683417 |
1 |
|
|
T20 |
808 |
|
T21 |
28186 |
|
T1 |
14067 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8915696 |
1 |
|
|
T19 |
240 |
|
T20 |
1276 |
|
T21 |
81141 |
auto[1] |
6579837 |
1 |
|
|
T20 |
1015 |
|
T21 |
78103 |
|
T1 |
37259 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1967968 |
1 |
|
|
T20 |
94 |
|
T21 |
26086 |
|
T1 |
11538 |
auto[1] |
auto[0] |
auto[1] |
1350133 |
1 |
|
|
T20 |
468 |
|
T21 |
14875 |
|
T1 |
7038 |
auto[1] |
auto[1] |
auto[0] |
1928452 |
1 |
|
|
T20 |
113 |
|
T21 |
23831 |
|
T1 |
11654 |
auto[1] |
auto[1] |
auto[1] |
1333284 |
1 |
|
|
T20 |
340 |
|
T21 |
13311 |
|
T1 |
7029 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |