Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8912750 |
1 |
|
|
T19 |
240 |
|
T20 |
1152 |
|
T21 |
80392 |
auto[1] |
6582783 |
1 |
|
|
T20 |
1139 |
|
T21 |
78852 |
|
T1 |
39728 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12813979 |
1 |
|
|
T19 |
240 |
|
T20 |
1249 |
|
T21 |
131366 |
auto[1] |
2681554 |
1 |
|
|
T20 |
1042 |
|
T21 |
27878 |
|
T1 |
16496 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8901273 |
1 |
|
|
T19 |
240 |
|
T20 |
1050 |
|
T21 |
82188 |
auto[1] |
6594260 |
1 |
|
|
T20 |
1241 |
|
T21 |
77056 |
|
T1 |
44208 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1950338 |
1 |
|
|
T20 |
105 |
|
T21 |
25151 |
|
T1 |
14149 |
auto[1] |
auto[0] |
auto[1] |
1341867 |
1 |
|
|
T20 |
573 |
|
T21 |
14252 |
|
T1 |
8252 |
auto[1] |
auto[1] |
auto[0] |
1962368 |
1 |
|
|
T20 |
94 |
|
T21 |
24027 |
|
T1 |
13563 |
auto[1] |
auto[1] |
auto[1] |
1339687 |
1 |
|
|
T20 |
469 |
|
T21 |
13626 |
|
T1 |
8244 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |