Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8910316 |
1 |
|
|
T19 |
240 |
|
T20 |
1136 |
|
T21 |
83617 |
auto[1] |
6585217 |
1 |
|
|
T20 |
1155 |
|
T21 |
75627 |
|
T1 |
36487 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12830717 |
1 |
|
|
T19 |
240 |
|
T20 |
1479 |
|
T21 |
131973 |
auto[1] |
2664816 |
1 |
|
|
T20 |
812 |
|
T21 |
27271 |
|
T1 |
14616 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8951554 |
1 |
|
|
T19 |
240 |
|
T20 |
1300 |
|
T21 |
83290 |
auto[1] |
6543979 |
1 |
|
|
T20 |
991 |
|
T21 |
75954 |
|
T1 |
40048 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1954081 |
1 |
|
|
T20 |
78 |
|
T21 |
26186 |
|
T1 |
13891 |
auto[1] |
auto[0] |
auto[1] |
1343706 |
1 |
|
|
T20 |
483 |
|
T21 |
14701 |
|
T1 |
7982 |
auto[1] |
auto[1] |
auto[0] |
1925082 |
1 |
|
|
T20 |
101 |
|
T21 |
22497 |
|
T1 |
11541 |
auto[1] |
auto[1] |
auto[1] |
1321110 |
1 |
|
|
T20 |
329 |
|
T21 |
12570 |
|
T1 |
6634 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |