Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8934298 |
1 |
|
|
T19 |
240 |
|
T20 |
1112 |
|
T21 |
83105 |
auto[1] |
6561235 |
1 |
|
|
T20 |
1179 |
|
T21 |
76139 |
|
T1 |
40173 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12824416 |
1 |
|
|
T19 |
240 |
|
T20 |
1344 |
|
T21 |
131288 |
auto[1] |
2671117 |
1 |
|
|
T20 |
947 |
|
T21 |
27956 |
|
T1 |
15370 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8935137 |
1 |
|
|
T19 |
240 |
|
T20 |
1047 |
|
T21 |
81314 |
auto[1] |
6560396 |
1 |
|
|
T20 |
1244 |
|
T21 |
77930 |
|
T1 |
41576 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1952364 |
1 |
|
|
T20 |
146 |
|
T21 |
25604 |
|
T1 |
13191 |
auto[1] |
auto[0] |
auto[1] |
1339161 |
1 |
|
|
T20 |
508 |
|
T21 |
14409 |
|
T1 |
7403 |
auto[1] |
auto[1] |
auto[0] |
1936915 |
1 |
|
|
T20 |
151 |
|
T21 |
24370 |
|
T1 |
13015 |
auto[1] |
auto[1] |
auto[1] |
1331956 |
1 |
|
|
T20 |
439 |
|
T21 |
13547 |
|
T1 |
7967 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |