Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8908843 |
1 |
|
|
T19 |
240 |
|
T20 |
1276 |
|
T21 |
79865 |
| auto[1] |
6586690 |
1 |
|
|
T20 |
1015 |
|
T21 |
79379 |
|
T1 |
38147 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14638355 |
1 |
|
|
T19 |
240 |
|
T20 |
2252 |
|
T21 |
149757 |
| auto[1] |
857178 |
1 |
|
|
T20 |
39 |
|
T21 |
9487 |
|
T1 |
6198 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8853019 |
1 |
|
|
T19 |
240 |
|
T20 |
1207 |
|
T21 |
77636 |
| auto[1] |
6642514 |
1 |
|
|
T20 |
1084 |
|
T21 |
81608 |
|
T1 |
46408 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2881193 |
1 |
|
|
T20 |
509 |
|
T21 |
36683 |
|
T1 |
20982 |
| auto[1] |
auto[0] |
auto[1] |
427479 |
1 |
|
|
T20 |
17 |
|
T21 |
4860 |
|
T1 |
3322 |
| auto[1] |
auto[1] |
auto[0] |
2904143 |
1 |
|
|
T20 |
536 |
|
T21 |
35438 |
|
T1 |
19228 |
| auto[1] |
auto[1] |
auto[1] |
429699 |
1 |
|
|
T20 |
22 |
|
T21 |
4627 |
|
T1 |
2876 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |